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HD74HC131 PDF даташит

Спецификация HD74HC131 изготовлена ​​​​«Hitachi Semiconductor» и имеет функцию, называемую «3-to-8-line Decoder/Demultiplexer with Edge-Triggered Address Registers».

Детали детали

Номер произв HD74HC131
Описание 3-to-8-line Decoder/Demultiplexer with Edge-Triggered Address Registers
Производители Hitachi Semiconductor
логотип Hitachi Semiconductor логотип 

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HD74HC131 Даташит, Описание, Даташиты
HD74HC131
3-to-8-line Decoder/Demultiplexer with Edge-Triggered
Address Registers
Description
The HD74HC131 is 3-to-8 linedecoder. It has Address select inputs (A,B,C) and D type register.
Address select data store to D type registers, during the positive going transition of the clock pulse.
Output control (G 1, G2) are independent of select input and CLK input, and when G1 is low or G2 = High,
all outputs is high.
Features
High Speed Operation: tpd (CLK to Y) = 20 ns typ (CL = 50 pF)
High Output Current: Fanout of 10 LSTTL Loads
Wide Operating Voltage: VCC = 2 V to 6 V
Low Input Current: 1 µA max
Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)









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HD74HC131 Даташит, Описание, Даташиты
HD74HC131
Function Table
Inputs
Enable
Select
Outputs
CLK G1 G2
C
B
A
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
XX H X X X H H H H H H H H
XL X X X X H H H H H H H H
H L L L L L H H HH H HH
H L L L H HL H HH H HH
H L L H L HH L HH H HH
H L L H H HH H L H H HH
H L HL L HH H HL H HH
H L HL H HH H HH L HH
H L HH L HH H HH H L H
H L HH H HH H HH H HL
LH
L
XX
X
Outputs corresponding to stored address, L; all others H
Pin Arrangement
A1
B2
C3
CLK 4
G2 5
G1 6
Y7 7
GND 8
(Top view)
16 VCC
15 Y0
14 Y1
13 Y2
12 Y3
11 Y4
10 Y5
9 Y6
2









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HD74HC131 Даташит, Описание, Даташиты
Logic Diagram
A
B
C
CLK
G2
G1
HD74HC131
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
3










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