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Número de pieza | HD74HC166 | |
Descripción | Parallel-load 8-bit Shift Register | |
Fabricantes | Hitachi Semiconductor | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de HD74HC166 (archivo pdf) en la parte inferior de esta página. Total 10 Páginas | ||
No Preview Available ! HD74HC166
Parallel-load 8-bit Shift Register
Description
This device is an 8-bit shift register with an output from the last stage. Data may be loaded into the register
either in parallel or in serial form. When the Shift/Load input is low, the data is loaded asynchronously in
parallel. When the Shift/Load input is high, the data is loaded serially on the rising edge of either clock
inhibit or Clock. Clear is asynchronous and active-low.
The 2-input NOR clock may be used either by combining two independent clock sources or by designating
one of the clock inputs to act as a clock inhibit.
Features
• High Speed Operation: tpd (Clock to QH) = 14 ns typ (CL = 50 pF)
• High Output Current: Fanout of 10 LSTTL Loads
• Wide Operating Voltage: VCC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
Function Table
Inputs
Clear
L
H
H
H
H
H
Shift/Load
X
X
L
H
H
X
Clock Inhibit Clock
XX
LL
L
L
L
H
Serial
X
X
X
H
L
X
Parallel
A ··· H
X
X
a ··· h
X
X
X
Internal Outputs
QA QB
LL
QA0
QB0
ab
H QAn
L QAn
QA0
QB0
Output
QH
L
QH0
h
QGn
QGn
QH0
1 page HD74HC166
AC Characteristics (CL = 50 pF, Input tr = tf = 6 ns)
Ta = 25°C
Ta = –40 to
+85°C
Item
Maximum clock
frequency
Symbol
f max
VCC (V)
2.0
4.5
Min Typ Max Min
——5 —
— — 25 —
Max Unit Test Conditions
4 MHz
20
6.0 — — 29 — 24
Propagation delay tPHL
time
t PLH
2.0 — — 175 — 220 ns Clock to QH
4.5 — 14 35 — 44
6.0 — — 30 — 37
tPHL 2.0 — — 150 — 190 ns Clear to QH
4.5 — 12 30 — 38
6.0 — — 26 — 33
Setup time
tsu 2.0 150 — — 190 — ns Shift/Load to Clock
4.5 30 2 — 38 —
6.0 26 — — 33 —
2.0 100 — — 125 — ns Data to Clock
4.5 20 1 — 25 —
6.0 17 — — 21 —
Hold time
th 2.0 5 — — 5 — ns Clock to Data
4.5 5 0 — 5 —
6.0 5 — — 5 —
Pulse width tw 2.0 80 — — 100 — ns Clock, Clear
4.5 16 6 — 20 —
6.0 14 — — 17 —
Output rise/fall
time
t TLH
t THL
2.0 — — 75 — 95 ns
4.5 — 5 15 — 19
6.0 — — 13 — 16
Input capacitance Cin — — 5 10 — 10 pF
5
5 Page |
Páginas | Total 10 Páginas | |
PDF Descargar | [ Datasheet HD74HC166.PDF ] |
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