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Número de pieza | HD74HC294 | |
Descripción | Programmable Frequency Divider/Digital Timer | |
Fabricantes | Hitachi Semiconductor | |
Logotipo | ||
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No Preview Available ! HD74HC292/HD74HC294
Programmable Frequency Divider/Digital Timer
Description
This device divides the incoming clock frequency by a number (a power of 2) that is preset by the
Programming inputs. It has two Clock inputs, either of which may be used as a clock inhibit. The device
also has an active-low Reset, which initializes the internal flip-flop states. Test Point outputs (TP1, TP2,
TP3) are provided with HD74HC292 to facilitate incoming inspections.
Test Point output is provided with HD74HC294 to facilitate incoming inspections.
Features
• High Speed Operation: tpd (Clock to Q) = 16 ns typ (CL = 50 pF)
• High Output Current: Fanout of 10 LSTTL Loads
• Wide Operating Voltage: VCC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
Function Table
CLR
L
H
H
H
H
CLK1
X
L
H
X
CLK2
X
L
X
H
Q Output Mode
Cleared to L
Count
Count
Inhibit
Inhibit
1 page Logic Diagram
HD74HC292
CLR
CLK1
CLK2
RR
CK
0
1
14
13
12
11
10
A9
B2
C4
D8
8
E6 7
6
5
4
3
2
HD74HC292/HD74HC294
R R MC
CK
RR
DDD
R R MC
CK
RR
DDDD
R R MC
CK
RR
DDD
R R MC
CK
RR
DDD
TP1
TP2
TP3
Q
5
5 Page 9.9
10.3 Max
16
9
1
1.27
8
0.635 Max
*0.42 ± 0.08
0.40 ± 0.06
0.15
0.25 M
*Dimension including the plating thickness
Base material dimension
Unit: mm
6.10
+
–
0.10
0.30
1.08
0.60
+
–
0.67
0.20
0° – 8°
Hitachi Code
JEDEC
EIAJ
Weight (reference value)
FP-16DN
Conforms
Conforms
0.15 g
11 Page |
Páginas | Total 12 Páginas | |
PDF Descargar | [ Datasheet HD74HC294.PDF ] |
Número de pieza | Descripción | Fabricantes |
HD74HC292 | Programmable Frequency Divider/Digital Timer | Hitachi Semiconductor |
HD74HC294 | Programmable Frequency Divider/Digital Timer | Hitachi Semiconductor |
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