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H9CKNNN8GTMPLR PDF даташит

Спецификация H9CKNNN8GTMPLR изготовлена ​​​​«Hynix» и имеет функцию, называемую «8Gb LPDDR3».

Детали детали

Номер произв H9CKNNN8GTMPLR
Описание 8Gb LPDDR3
Производители Hynix
логотип Hynix логотип 

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H9CKNNN8GTMPLR Даташит, Описание, Даташиты
168ball FBGA Specification
8Gb LPDDR3 (x32)
This document is a general product description and is subject to change without notice. SK hynix does not assume any responsibility
for use of circuits described. No patent licenses are implied.
Rev 1.1 / Oct. 2013
1









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H9CKNNN8GTMPLR Даташит, Описание, Даташиты
Document Title
FBGA
8Gb (x32) LPDDR3
H9CKNNN8GTMPLR
LPDDR3-S8B 8Gb(x32)
Revision History
Revision No.
History
0.1 - Initial Draft
0.2 - Corrected tWLS and tWLH in AC Timing Parameters
0.3 - Corrected a typo
0.4 - Added DRAM speed 1866Mbps to ORDERING INFORMATION
1.0
Final Version
- Updated IDD specification and Input/Output Capacitance
1.1 - Added DRAM speed 1866Mbps
Draft Date
May. 2013
Jun. 2013
Jun. 2013
Jul. 2013
Remark
Preliminary
Preliminary
Preliminary
Preliminary
Aug. 2013
Oct. 2013
Rev 1.1 / Oct. 2013
2









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H9CKNNN8GTMPLR Даташит, Описание, Даташиты
H9CKNNN8GTMPLR
LPDDR3-S8B 8Gb(x32)
FEATURES
[ FBGA ]
Operation Temperature
- (-30)oC ~ 105oC
Package
- 168-ball FBGA - 12.0x12.0mm2, 0.70t, 0.50mm pitch
- Lead & Halogen Free
[ LPDDR3 ]
VDD1 = 1.8V (1.7V to 1.95V)
VDD2, VDDCA and VDDQ = 1.2V (1.14V to 1.30)
HSUL_12 interface (High Speed Unterminated Logic 1.2V)
Double data rate architecture for command, address and data Bus;
- all control and address except CS_n, CKE latched at both rising and falling edge of the clock
- CS_n, CKE latched at rising edge of the clock
- two data accesses per clock cycle
Differential clock inputs (CK_t, CK_c)
Bi-directional differential data strobe (DQS_t, DQS_c)
- Source synchronous data transaction aligned to bi-directional differential data strobe (DQS_t, DQS_c)
- Data outputs aligned to the edge of the data strobe (DQS_t, DQS_c) when READ operation
- Data inputs aligned to the center of the data strobe (DQS_t, DQS_c) when WRITE operation
DM masks write data at the both rising and falling edge of the data strobe
Programmable RL (Read Latency) and WL (Write Latency)
Programmable burst length: 8
Auto refresh and self refresh supported
All bank auto refresh and per bank auto refresh supported
Auto TCSR (Temperature Compensated Self Refresh)
PASR (Partial Array Self Refresh) by Bank Mask and Segment Mask
DS (Drive Strength)
DPD (Deep Power Down)
ZQ (Calibration)
ODT (On Die Termination)
Rev 1.1 / Oct. 2013
3










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