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PDF HD74HC589 Data sheet ( Hoja de datos )
| Número de pieza | HD74HC589 | |
| Descripción | 8-bit Serial of Parallel-input/Serial-output Shift Register(with 3-state outputs) | |
| Fabricantes | Hitachi Semiconductor | |
| Logotipo |  |
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HD74HC589
8-bit Serial of Parallel-input/Serial-output Shift Register
(with 3-state outputs)
Description
The HD74HC589 is similar in function to the HD74HC597, which is not a 3-state device.
This device consists of an 8-bit storage latch which feeds parallel data to an 8-bit shift register. Data can
also be loaded serially (see Function Table). The shift register output, OH, is a three-state output, allowing
this device to be used in bus-oriented systems.
Features
• High Speed Operation: tpd (Shift Clock to QH) = 15 ns typ (CL = 50 pF)
• High Output Current: Fanout of 15 LSTTL Loads
• Wide Operating Voltage: VCC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
Function Table
Latch Clock
LCK
Shift Clock
SCK
X
X
XX
L, H,
X
L, H,
Serial Shift/
Parallel Load
X
L
L
X
H
Output Enable Function
OE
X Data are loaded into input latches
L Data are loaded from input into shift
registers
L Data are transfered from input
latches to shift registers
H Outputs are disabled
L Serial shift Qn = Qn – 1, Q0 = SER
1 page  
HD74HC589
AC Characteristics (CL = 50 pF, Input tr = tf = 6 ns)
Ta = 25°C
Ta = –40 to
+85°C
Item
Maximum clock
frequency
Symbol
f max
VCC (V)
2.0
4.5
Min Typ Max Min
——5 —
— — 27 —
Max Unit Test Conditions
4 MHz
21
6.0 — — 32 — 25
Propagation delay tPLH
time
t PHL
2.0 — — 200 — 250 ns Latch clock to QH
4.5 — 20 40 — 50
6.0 — — 34 — 43
tPLH 2.0 — — 175 — 220 ns Shift clock to QH
tPHL 4.5 — 15 35 — 44
6.0 — — 30 — 37
tPLH 2.0 — — 175 — 220 ns Serial shift/prallel load to QH
tPHL 4.5 — 16 35 — 44
6.0 — — 30 — 37
Output enable
time
t ZL
t ZH
2.0 — — 150 — 190 ns
4.5 — 9 30 — 38
6.0 — — 26 — 33
Output disable
time
t LZ
t HZ
2.0 — — 150 — 190 ns
4.5 — 14 30 — 38
6.0 — — 26 — 33
Pulse width tw 2.0 80 — — 100 — ns
4.5 16 8 — 20 —
6.0 14 — — 17 —
Setup time
tsu 2.0 100 — — 125 — ns Data to latch clock
4.5 20 1 — 25 —
6.0 17 — — 21 —
tsu 2.0 100 — — 125 — ns SA to shift clock
4.5 20 — — 25 —
6.0 17 — — 21 —
tsu 2.0 100 — — 125 — ns Serial shift/parallel load to
4.5 20 — — 25 —
shift clock
6.0 17 — — 21 —
5
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet HD74HC589.PDF ] | |
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