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PDF HD74HC673 Data sheet ( Hoja de datos )
| Número de pieza | HD74HC673 | |
| Descripción | 16-bit Shift Register | |
| Fabricantes | Hitachi Semiconductor | |
| Logotipo |  |
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HD74HC673
16-bit Shift Register
Description
The HD74HC673 is a 16-bit shift register and a 16-bit storage register in a single 24-pin package. A three-
state input/output (data I/O) port to the shift register allows serial entry and/or reading of data. The storage
register is connected in a parallel data loop with the shift register and may be asynchronously cleared by
taking the store-clear input low. The storage register may be parallel loaded with shift-register data to
provide shift-register status via the parallel outputs. The shift register can be parallel loaded with the
storage-register data upon command.
A high logic level at the chip-select (CS) input disables both the shift-register clock and the storage register
clock and places the data I/O in the high-impedance state. The store-clear function is not disabled by the
chip select.
Caution must be exercised to prevent false clocking of either the shift register or the storage register via the
chip-select input. The shift clock should be low during the low-to-high transition of chip select and the
store clock should be low during the high-to-low transition of chip select.
Features
• High Speed Operation: tpd (MODE/STRCLK to Y) = 23 ns typ (CL = 50 pF)
• High Output Current: Fanout of 15 LSTTL Loads (Q15 output)
• Wide Operating Voltage: VCC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
1 page  
HD74HC673
AC Characteristics (CL = 50 pF, Input tr = tf = 6 ns)
Ta = 25°C
Ta = –40 to
+85°C
Item
Maximum clock
frequency
Symbol
f max
VCC (V)
2.0
4.5
Min Typ Max Min
——5 —
— — 27 —
Max Unit Test Conditions
4 MHz
21
6.0 — — 32 — 25
Propagation delay tPLH
time
t PHL
2.0 — — 200 — 250 ns STRCLR to Y
4.5 — 23 40 — 50
6.0 — — 34 — 43
tPLH 2.0 — — 200 — 250 ns Mode/STRCLK to Y
tPHL 4.5 — 23 40 — 50
6.0 — — 34 — 43
tPLH 2.0 — — 200 — 250 ns SHCLK to SER/Q15
tPHL 4.5 — 19 40 — 50
6.0 — — 34 — 43
Output enable
time
t ZH
t ZL
2.0 — — 150 — 190 ns
4.5 — — 30 — 38
6.0 — — 26 — 33
Output disable
time
t HZ
t LZ
2.0 — — 150 — 190 ns
4.5 — — 30 — 38
6.0 — — 26 — 33
Pulse width tw 2.0 80 — — 100 — ns
4.5 16 6 — 20 —
6.0 14 — — 17 —
Setup time
tsu 2.0 100 — — 125 — ns SER/Q15 to SH CLK
4.5 20 1 — 25 —
6.0 17 — — 21 —
tsu 2.0 100 — — 125 — ns CS to R/W
4.5 20 7 — 25 —
6.0 17 — — 21 —
Hold time
th 2.0 5 — — 5 — ns SH CLK to SER/Q15
4.5 5 0 — 5 —
6.0 5 — — 5 —
5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet HD74HC673.PDF ] | |
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