(PDF) HD74HCT138 Datasheet - 3-to-8-line Decoder/Demultiplexer

Número de pieza	HD74HCT138
Descripción	3-to-8-line Decoder/Demultiplexer
Fabricantes	Hitachi Semiconductor
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No Preview Available ! HD74HCT138 3-to-8-line Decoder/Demultiplexer Description The HD74HCT138 has 3 binary select inputs (A, B, and C). If the device is enabled these inputs determine which one of the eight normally high outputs will go low. Two active low and one active high enables (G1, G2A and G2B) are provided to ease the cascading of decoders. Features • LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility • High Speed Operation: tpd (A, B, C to Y) = 18.5 ns typ (CL = 50 pF) • High Output Current: Fanout of 10 LSTTL Loads • Wide Operating Voltage: VCC = 4.5 to 5.5 V • Low Input Current: 1 µA max • Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) 1 page 10.06 10.5 Max 16 9 18 0.80 Max 1.27 0.42 ± 0.08 0.40 ± 0.06 0.15 0.12 M Dimension including the plating thickness Base material dimension Unit: mm 7.80 + – 0.20 0.30 1.15 0.70 ± 0.20 0° – 8° Hitachi Code JEDEC EIAJ Weight (reference value) FP-16DA — Conforms 0.24 g 5 Page

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PDF HD74HCT138 Data sheet ( Hoja de datos )