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PDF HD74LV166A Data sheet ( Hoja de datos )
| Número de pieza | HD74LV166A | |
| Descripción | Parallel-Load 8-bit Shift Register | |
| Fabricantes | Hitachi Semiconductor | |
| Logotipo |  |
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HD74LV166A
Parallel-Load 8-bit Shift Register
ADE-205-268 (Z)
1st Edition
March 1999
Description
The HD74LV166A is 8-bit shift register with an output from the last stage. Data may be loaded into the
register either in parallel or in serial form. When the Shift/Load input is low, the data is loaded
asynchronously in parallel. When the Shift/Load input is high, the data is loaded serially on the rising edge
of either clock inhibit or Clock. Clear is asynchronous and active-low.
The 2-input NOR clock may be used either by combining two independent clock sources or by designating
one of the clock inputs to act as a clock inhibit.
Low-voltage and high-speed operation is suitable for the battery-powered products (e.g., notebook
computers), and the low-power consumption extends the battery life.
Features
• VCC = 2.0 V to 5.5 V operation
• All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)
• All outputs VO (Max.) = 5.5 V (@VCC = 0 V)
• Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
• Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25°C)
• Output current ±6 mA (@VCC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V)
1 page  
HD74LV166A
Logic Diagram
A SER B C D E F G CLR H SH/LD CLK CLK INH
R CP S
CD Q
R CP S
CD Q
QH
5
5 Page 
Operating Characteristics
• CL = 50 pF
Item
Power
dissipation
capacitance
Symbol
CPD
VCC (V)
3.3
5.0
Ta = 25°C
Min Typ
— 36.1
— 37.5
Max
—
—
HD74LV166A
Unit Test Conditions
pF f = 10 MHz
Test Circuit
Measurement point
CL*
Note: CL includes the probe and jig capacitance.
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet HD74LV166A.PDF ] | |
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