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HDSP-4200 PDF даташит

Спецификация HDSP-4200 изготовлена ​​​​«Agilent(Hewlett-Packard)» и имеет функцию, называемую «20 mm (0.8 inch) Seven Segment Displays».

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Номер произв HDSP-4200
Описание 20 mm (0.8 inch) Seven Segment Displays
Производители Agilent(Hewlett-Packard)
логотип Agilent(Hewlett-Packard) логотип 

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HDSP-4200 Даташит, Описание, Даташиты
Low Cost Gigabit Rate
Transmit/Receive Chip Set with
TTL I/Os
Preliminary Technical Data
HDMP-1022 Transmitter
HDMP-1024 Receiver
Features
Transparent, Extended
Ribbon Cable Replacement
Implemented in a Low Cost
Aluminum M-Quad 80
Package
High-Speed Serial Rate
150-1500 MBaud
Standard TTL Interface
16, 17, 20, or 21 Bits Wide
Reliable Monolithic Silicon
Bipolar Implementation
On-Chip Phase-Locked
Loops
- Transmit Clock Generation
- Receive Clock Extraction
Applications
Backplane/Bus Extender
Video, Image Acquisition
Point to Point Data Links
Implement SCI-FI Standard
Implement Serial HIPPI
Specification
Description
The HDMP-1022 transmitter and
the HDMP-1024 receiver are used
to build a high-speed data link for
point-to-point communication.
The monolithic silicon bipolar
transmitter chip and receiver chip
are each provided in a standard
aluminum M-Quad 80 package.
From the user’s viewpoint, these
products can be thought of as
providing a “virtual ribbon cable”
interface for the transmission of
data. Parallel data (a frame)
loaded into the Tx (transmitter)
chip is delivered to the Rx
(receiver) chip over a serial
channel, which can be either a
coaxial copper cable or optical
link.
The chip set hides from the user
all the complexity of encoding,
multiplexing, clock extraction,
demultiplexing and decoding.
Unlike other links, the phase-
locked-loop clock extraction
circuit also transparently provides
for frame synchronization–the
user is not troubled with the
periodic insertion of frame syn-
chronization words. In addition,
the dc balance of the line code is
automatically maintained by the
chip set. Thus, the user can
transmit arbitrary data without
restriction. The Rx chip also
includes a state-machine con-
troller (SMC) that provides a
startup handshake protocol for
the duplex link configuration.
The serial data rate of the T/R link
is selectable in four ranges (see
tables on page 5), and extends
from 120 Mbits/s up to 1.25
Gbits/s. The parallel data interface
is 16 or 20 bit TTL, pin select-
able. A flag bit is available and
can be used as an extra 17th or
21st bit under the user’s control.
The flag bit can also be used as an
even or odd frame indicator for
dual-frame transmission. If not
used, the link performs expanded
error detection.
The serial link is synchronous,
and both frame synchronization
and bit synchronization are main-
tained. When data is not available
to send, the link maintains
synchronization by transmitting
fill frames. Two (training) fill
frames are reserved for
handshaking during link startup.
User control space is also sup-
ported. If Control Available is
asserted at the Tx chip, the least
significant 14 or 18 bits of the
data are sent and the Rx Control
Available line will indicate the
data as a Control Word.
It is the intention of this data
sheet to provide the design
engineer all of the information
regarding the HDMP-1022/1024
chipset necessary to design this
product into their application. To
assist you in using this data sheet,
the following Table of Contents is
provided.
(5/97)
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HDSP-4200 Даташит, Описание, Даташиты
Typical Applications
The HDMP-1022/1024 chipset
was designed for ease of use and
flexibility. This allows the
customer to tailor the use of this
product, through the configura-
tion of the link, based on his
specific system requirements and
application needs. Typical
applications range from backplane
and bus extension to digital video
transmission.
CLK
Tx Rx
A) 16/20 BIT SIMPLEX TRANSMISSION
CLK
MUX
CLK
Tx
Rx DEMUX
CLK
B) 32/40 BIT SIMPLEX TRANSMISSION
Low latency bus extension of a 16
or 20 bit wide data bus may be
achieved using the standard
duplex configuration (see Figure
1d). In full duplex, the HDMP-
1022/1024 chipset handles all of
the issues of link startup, main-
tenance, and simple error
detection.
CLK
Tx
Rx
CLK
CLK
Tx
Rx
CLK
C) 32/40 BIT SIMPLEX TRANSMISSION
WITH HIGH CLOCK RATES
If the bus width is 32 or 40 bits
wide, the HDMP-1022/1024
chipset is capable of sending the
large data frame as two separate
frame segments, as shown in
Figure 1b. In this mode, called
Double Frame Mode, the FLAG
bit is used by the transmitter and
receiver to indicate the first or
second frame segment
(Figure 19). The HDMP-1022/
1024 chipset in Double Frame
Mode may also be configured in
full duplex to achieve a 32/40 bit
wide bus extension.
For digital video transmission,
simplex links are more common.
The HDMP-1022/1024 chipset
can transmit 16 to 21 bits of
parallel data in standard or
broadcast simplex mode.
Additionally, 32 to 40 bit wide
data can be transmitted over a
single line (in Double Frame
Mode) or two parallel lines, as in
Figure 1c.
CLK
CLK
Tx Rx
CLK
Rx Tx
CLK
D) 16/20 BIT DUPLEX TRANSMISSION
CLK
Tx
Rx
CLK
Rx
CLK
Rx
CLK
E) SIMPLEX BROADCAST TRANSMISSION
Figure 1. Various Configurations Using the HDMP-1022/1024.
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HDSP-4200 Даташит, Описание, Даташиты
For timing diagrams for the
standard configurations, see the
Appendix section entitled Link
Configuration Examples.
The HDMP-1022/1024 chipset
can support serial transmission
rates from 150 MBd to 1.5 GBd
for each of these configurations.
The chipset requires the user to
input the link data rate by assert-
ing DIV1 and DIV0 accordingly.
To determine the DIV1/DIV0
setting necessary for each
application, refer to the section:
Setting the Operating Data Rate
Range below.
Setting the Operating
Data Rate Range
The HDMP-1022/1024 chipset
can operate from 150 MBaud to
1500 MBaud. It is divided into
four operating data ranges with
each range selected by setting
DIV1 and DIV0 as shown in the
tables on the following page.
The purpose of following example
is to help in understanding and
using these tables. This specific
example uses the table in Figure 3
entitled “Typical 20-bit Mode Data
Rates.”
It is desired to transmit a 20 bit
parallel word operating at 55 MHz
(55 MWord/sec). Both the Tx and
Rx must be set to a range that
covers this word rate. According
to the table entitled “Typical
Operating Rates for 20 Bit Mode”
on the next page, a setting of
DIV1/DIV0 = logic ‘0/0’ allows a
parallel input word rate of 29.2 to
62.5 MHz . This setting easily
accommodates the required 55
MHz word rate. The user serial
data rate can be calculated as:
Serial
Data Rate
= (–2–0––b–it–) (5––5–M––w–)
word
sec
= 1100 MBits/sec
The baud rate includes an
additional 4 bits that G-LINK
transmits for link control and
error detection. The serial baud
rate is calculated as:
Serial
Baud Rate
= (2––4–b––it–s) (5––5–M––w–)
word
sec
= 1320 MBaud
The 55 MHz example is one in
which the parallel word rate
provides only one possible DIV1/
DIV0 setting.
Some applications may have a
parallel word rate that seems to fit
two ranges. As an example, a 35
MHz (35 MWord/s) parallel data
rate falls within two ranges (DIV0/
DIV1 = 0/0 and DIV0/DIV1 = 0/
1) in 20 Bit Mode. Per the table, a
setting of DIV1/DIV0 = 0/1 gives
an upper rate of 37.5 MHz , while
a setting of DIV1/DIV0 = 0/0
gives a lower rate of 29.2 MHz.
These transition data rates are
stated in the tables as typical
values and may vary between
individual parts. Each transmitter/
receiver has continuous band
coverage across its entire 150 to
1500 MBaud range and has
overlap between ranges. Each
transmitter/receiver will permit a
35 MHz parallel data rate, but it is
suggested that DIV0 be a jumper
that can be set either to logic ‘1’
(open) or logic ‘0’ (ground). This
allows the design to accommodate
both ranges for maximum flexibil-
ity. This technique is recom-
mended whenever operating near
the maximum and minimum of
two word rate ranges. The above
information also applies to the
HDMP-1022/1024 chipset when
operating in 16 bit mode.
PRE-RELEASE
PRODUCT DISCLAIMER
This product is in development at the
Hewlett-Packard CSSD in San Jose,
California. Until Hewlett-Packard
releases this product for general
sales, HP reserves the right to alter
specifications, features, capabilities,
functions, manufacturing release
dates, and even general availability of
the product at any time.
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