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PDF HDH-12820CID Data sheet ( Hoja de datos )
| Número de pieza | HDH-12820CID | |
| Descripción | Couplers with Connectors (H Type) | |
| Fabricantes | Hirose Electric | |
| Logotipo |  |
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Fibre Channel Transceiver Chip
Technical Data
HDMP-1526 Transceiver
Features
• ANSI X3.230-1994 Fibre
Channel Compatible (FC-0)
• Supports Full Speed
(1062.5 MBd) Fibre Channel
• Conforms to “Fibre Channel
10-Bit Interface”
Specification
• Transmitter and Receiver
Functions Incorporated onto
a Single IC
• 10-Bit Wide Parallel TTL
Compatible I/Os
• Single +5.0 V Power Supply
Applications
• 1062.5 MBd Fibre Channel
Interface
• Mass Storage System I/O
Channel
• Work Station/Server I/O
Channel
• High Speed Proprietary
Interface
Description
The HDMP-1526 transceiver is a
single silicon bipolar integrated
circuit packaged in an EDQuad
package. It provides a low-cost,
low-power physical layer solution
for 1062.5 MBd Fibre Channel or
proprietary link interfaces. It
provides complete FC-0 func-
tionality for copper transmission,
incorporating both the Fibre
Channel FC-0 transmit and
receive functions into a single
device.
This chip is used to build a high-
speed interface (as shown in
Figure 1) while minimizing board
space, power and cost. It is
compatible with both the ANSI
X3.230-1994 document and the
“Fibre Channel 10-bit Interface”
specification.
The transmitter section accepts
10-bit wide parallel TTL data and
multiplexes this data into a high-
speed serial data stream. The
parallel data is expected to be
8B/10B encoded data, or
equivalent. This parallel data is
latched into the input register of
the transmitter section on the
rising edge of the 106.25 MHz
reference clock (used as the
transmit byte clock).
The transmitter section’s PLL
locks to this user supplied 106.25
MHz byte clock. This clock is
multiplied by 10, to generate the
1062.5 MHz serial signal clock
used to generate the high-speed
output. The high-speed outputs
are capable of interfacing directly
to copper cables for electrical
transmission or to a separate
fiber-optic module for optical
transmission.
The receiver section accepts a
serial electrical data stream at
1062.5 MBd and recovers the
original 10-bit wide parallel data.
The receiver PLL locks onto the
incoming serial signal and
recovers the high-speed serial
clock and data. The serial data is
converted back into 10-bit
parallel data, recognizing the
8B/10B comma character to
establish byte alignment.
The recovered parallel data is
presented to the user at TTL
compatible outputs. The receiver
section also recovers two 53.125
MHz receiver byte clocks that are
180 degrees out of phase with
each other. The parallel data is
aligned with the rising edge of
alternating clocks.
The transceiver provides for on-
chip local loop-back functionality,
controlled through an external
input pin. Additionally, the byte
synchronization feature may be
disabled. This may be useful in
proprietary applications that use
alternative methods to align the
parallel data.
682 5964-6897E (5/96)
1 page  
HDMP-1526 (Receiver Section)
Timing Characteristics
TC = 0°C to +85°C, VCC = 4.5 V to 5.25 V
Symbol
Parameter
b_sync[1,2]
Bit Sync Time
f_lock[2]
Frequency Lock Time
(from Time of Setting -LCKREF = 0)
f_lock_rate[2] Frequency Lock Rate (when -LCKREF = 0)
tvalid_before
Time Data Valid Before Rising Edge of RBC
tvalid_after
Time Data Valid After Rising Edge of RBC
tduty
tA-B[3]
t_rxlat[4]
RBC Duty Cycle
Rising Edge Time Difference
Receiver Latency
Units
bits
µsec
Min.
kHz/µsec
nsec
nsec
%
nsec
nsec
bits
3
1.5
40
8.9
Typ.
200
5.8
3.3
9.4
25.0
26.6
Max.
2500
500
60
9.9
33.9
36
Notes:
1. This is the recovery time for input phase jumps, per the FC-PH specification Ref 4.1, Sec 5.3.
2. Tested using CPLL = 0.01 µF.
3. The RBC clock skew is calculated as tA-B(max) - tA-B(min).
4. The receiver latency, as shown in Figure 5, is defined as the time between receiving the first serial bit of a parallel data word (as
defined as the first edge of the first serial bit) and the clocking out of that parallel word (defined by the rising edge of the receive
byte clock, either RBC1 or RBC0).
t-VALID BEFORE
RBC1
t-VALID AFTER
RX[0]-RX[9]
,,,,,,,,,BYTSYNC
K28.5
DATA
DATA
DATA
DATA
1.4 V
2.0 V
0.8 V
2.0 V
0.8 V
RBC0
Figure 5. Receiver Section.
1.4 V
DATA BYTE C
DATA BYTE D
± DIN R5 R6 R7 R8 R9 R0 R1 R2 R3 R4 R5 R6 R7 R8 R9
t_RXLAT
,, ,,RX[0]-RX[9]
DATA BYTE A
R2 R3 R4 R5
DATA BYTE D
RBC1/0
1.4 V
Figure 6. Receiver Latency.
686
5 Page 
TRx I/O Definition
Name
GND_TXTTL
TX[0]
TX[1]
TX[2]
TX[3]
TX[4]
TX[5]
TX[6]
TX[7]
TX[8]
TX[9]
VCC_TXTTL
GND_TXA
Pin
1
14
2
3
4
6
7
8
9
11
12
13
5
10
15
Type
S
I-TTL
S
S
TXCAP1
TXCAP0
VCC_TXA
16
17
18
C
S
LOOPEN 19 I-TTL
VCC_TX
GND
REFCLK
20 S
59
21 S
25
58
22 I-TTL
VCC_RX
ENBYTSYNC
23
28
57
24
S
I-TTL
-LCKREF
692
27 I-TTL
Signal
TTL Transmitter Ground: Normally 0 volts. Used for the TTL input cells
of the transmitter section.
Data Inputs: One, 10 bit, pre-encoded data byte. TX[0] is the first bit
transmitted. TX[0] is the least significant bit.
TTL Power Supply: Normally 5 volts. Used for all TTL transmitter input
buffer cells.
Analog Ground: Normally 0 volts. Used to provide a clean ground plane
for the PLL and high-speed analog cells.
Loop Filter Capacitor: A loop filter capacitor must be connected across
the TXCAP1 and TXCAP0 pins (typical value = 0.01 µF).
Analog Power Supply: Normally 5 volts. Used to provide a clean supply
line for the PLL and high-speed analog cells.
Loopback Enable Input: When set high, the high-speed serial signal is
internally wrapped from the transmitter’s serial loopback outputs back
to the receiver’s loopback inputs. Also, when in loopback mode, the
± DOUT outputs are held static. When set low, ± DOUT outputs and
± DIN inputs are active.
Logic Power Supply: Normally 5 volts. Used for internal transmitter
PECL logic. It should be isolated from the noisy TTL supply as well as
possible.
Logic Ground: Normally 0 volts. This ground is used for internal PECL
logic. It should be isolated from the noisy TTL ground as well as possible.
Reference Clock and Transmit Byte Clock: A 106.25 MHz clock supplied
by the host system. The transmitter section accepts this signal as the
frequency reference clock. It is multiplied by 10 to generate the serial bit
clock and other internal clocks. The transmit side also uses this clock as
the transmit byte clock for the incoming parallel data TX[0]..TX[9]. It
also serves as the reference clock for the receive portion of the
transceiver. When -LCKREF is activated, the receiver PLL frequency
locks to this reference signal.
Logic Power Supply: Normally 5 volts. Used for internal receiver PECL
logic. It should be isolated from the noisy TTL supply as well as possible.
Enable Byte Sync Input: When high, enables the internal byte sync
function to allow clock synchronization to a comma character (or a
K28.5 character) of positive disparity (0011111010). When the line is
low, the function is disabled and will not reset registers and clocks, or
strobe the BYTSYNC line.
Lock to Reference: When low, causes the PLL to acquire frequency lock
on the external reference, supplied at REFCLK.
11 Page | ||
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