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PDF HDSP-5300 Data sheet ( Hoja de datos )
| Número de pieza | HDSP-5300 | |
| Descripción | 14.2 mm (0.56 inch) Seven Segment Displays | |
| Fabricantes | ETC | |
| Logotipo |  |
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Fibre Channel Transceiver Chip
Technical Data
HDMP-1536 Transceiver
HDMP-1546 Transceiver
Features
• ANSI X3.230-1994 Fibre
Channel Compatible (FC-0)
• Supports Full Speed
(1062.5 MBd) Fibre Channel
• Compatible with “Fibre
Channel 10-Bit Interface”
Specification
• Low Power Consumption,
630 mW
• Transmitter and Receiver
Functions Incorporated onto
a Single IC
• Auto Frequency Lock
• Small Package Profile
HDMP-1536, 10x10 mm QFP
HDMP-1546, 14x14 mm QFP
• 10-Bit Wide Parallel TTL
Compatible I/Os
• Single +3.3 V Power Supply
Applications
• 1062.5 MBd Fibre Channel
Interface
• FC Interface for Disk Drives
and Arrays
• Mass Storage System I/O
Channel
• Work Station/Server I/O
Channel
• High Speed Proprietary
Interface
• High Speed Backplane
Interface
Description
The HDMP-1536/46 transceiver
is a single silicon bipolar
integrated circuit packaged in a
plastic QFP package. It provides
a low-cost, low-power physical
layer solution for 1062.5 MBd
Fibre Channel or proprietary link
interfaces. It provides complete
FC-0 functionality for copper
transmission, incorporating both
the Fibre Channel FC-0 transmit
and receive functions into a
single device.
This chip is used to build a high-
speed interface (as shown in
Figure 1) while minimizing board
space, power, and cost. It is
compatible with both the ANSI
X3.230-1994/AM 1 - 1996
document and the “Fibre Channel
10-bit Interface” specification.
The transmitter section accepts
10-bit wide parallel TTL data and
multiplexes this data into a high-
speed serial data stream. The
parallel data is expected to be
8B/10B encoded data, or
equivalent. This parallel data is
latched into the input register of
the transmitter section on the
rising edge of the 106.25 MHz
reference clock (used as the
transmit byte clock).
The transmitter section’s PLL
locks to this user supplied 106.25
MHz byte clock. This clock is
then multiplied by 10, to generate
the 1062.5 MHz serial signal
clock used to generate the high-
speed output. The high-speed
outputs are capable of interfacing
directly to copper cables for
electrical transmission or to a
separate fiber-optic module for
optical transmission.
The receiver section accepts a
serial electrical data stream at
1062.5 MBd and recovers the
original 10-bit wide parallel data.
The receiver PLL locks onto the
incoming serial signal and
recovers the high-speed serial
clock and data. The serial data is
696 5965-8113E (4/97)
1 page  
HDMP-1536/46 (Transmitter Section)
Timing Characteristics
TA[1] = 0°C to +60°C, VCC = 3.15 V to 3.45 V
Symbol
Parameter
tsetup
Setup Time
thold
t_txlat[2]
Hold Time
Transmitter Latency
Units
nsec
nsec
nsec
bits
Min.
2
1.5
Typ.
7.5
8.0
Max.
Notes:
1. Device tested and characterized under TA conditions specified, with TC monitored at approximately 20° higher than TA.
2. The transmitter latency, as shown in Figure 4, is defined as the time between the latching in of the parallel data word (as triggered
by the rising edge of the transmit byte clock, REFCLK) and the transmission of the first serial bit of that parallel word (defined by
the rising edge of the first bit transmitted).
REFCLK
,,,,,,,TX[0]-TX[9]
DATA
DATA
DATA
DATA
DATA
1.4 V
2.0 V
0.8 V
tsetup
thold
Figure 3. Transmitter Section Timing.
DATA BYTE A
DATA BYTE B
± DOUT T5 T6 T7 T8 T9 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T0 T1 T2 T3 T4 T5
t_txlat
,, ,,TX[0]-TX[9]
DATA BYTE B
DATA BYTE C
REFCLK
1.4 V
Figure 4. Transmitter Latency.
700
5 Page 
GND_TXTTL
TX[0]
TX[1]
TX[2]
VCC_TXTTL
TX[3]
TX[4]
TX[5]
TX[6]
VCC_TXTTL
TX[7]
TX[8]
TX[9]
GND_TXTTL
GND_TXA
TXCAP1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1 48
2 47
3 46
4 45
5 44
6 43
7
8
HDMP-15x6
42
41
9
xxxx-x Rz.zz
40
10 39
11 S YYWW 38
12 37
13 36
14 35
15 34
16 33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
RXCAP0
BYTSYNC
GND_RXTTL
RX[0]
RX[1]
RX[2]
VCC_RXTTL
RX[3]
RX[4]
RX[5]
RX[6]
VCC_RXTTL
RX[7]
RX[8]
RX[9]
GND_RXTTL
xxxx-x = WAFER LOT NUMBER–BUILD NUMBER
Rzz.zz = DIE REVISION
S = SUPPLIER CODE
YYWW = DATE CODE (YY = YEAR, WW = WORK WEEK)
COUNTRY = COUNTRY OF MANUFACTURE
(MARKED ON BACK OF DEVICE)
Figure 11. HDMP-1536/46 (TRx) Package Layout and Marking, Top View.
*Note: Pin 26 is designated as a “no connect” pin and should be left unconnected.
706
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet HDSP-5300.PDF ] | |
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