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PDF HCF4724B Data sheet ( Hoja de datos )
| Número de pieza | HCF4724B | |
| Descripción | 8 BIT ADDRESSABLE LATCH | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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HCC4724B
HCF4724B
. SERIAL DATA INPUT - ACTIVE PARALLEL
OUTPUT
. STORAGE REGISTER CAPABILITY - MASTER
CLEAR
. CAN FUNCTION AS DEMULTIPLEXER
. STANDARDIZED, SYMMETRICAL OUTPUT
CHARACTER
. 100% TESTED FOR QUIESCENT CURRENT
AT 20V
. MAXIMUM INPUT CURRENT OF 1µA AT 18V
. (full package-temperature range), 100nA AT 18V
AND 25oC
NOISE MARGIN (full package-temperature
.. range) = 1V AT VDD = 5V, 2V AT VDD = 10V, 2.5V
AT VDD = 15V
5V, 10V, AND 15V PARAMETRIC RATINGS
MEETS ALL REQUIREMENTS OF JEDEC TEN-
TATIVE STANDARD N. 13A, ” STANDARD
SPECIFICATIONS FOR DESCRIPTION OF ’ B
’ SERIES CMOS DEVICES ”
..APPLICATION
MULTI-LINE DECODERS
A/D CONVERTERS
DESCRIPTION
The HCC/HCF4724B 8-bit addressable latch is a
serial-input, parallel-output storage register that can
perform a variety of functions.
Data are inputted to a particular bit in the latch when
that bit is addressed (by means of inputs A0, A1, A2)
and when WRITE DISABLE is at low level. When
WRITE DISABLE is high, data entry is inhibited
however, all 8 outputs can be continuously read in-
dependent of WRITE DISABLE and address inputs.
A master RESET input is available, which resets all
bits to a logic ” 0 ” level when RESET and WRITE
DISABLE are at a high level. When RESET is at a
high level, and WRITE DISABLE is at a low level, the
latch acts as a 1-of-8 demultiplexer ; the bit that is
addressed has an active output which follows the
data input, while all unaddressed bits are held to a
logic ” 0 ” level.
8 BIT ADDRESSABLE LATCH
EY
(Plastic Package)
F
(Ceramic Package)
M1
(Micro Package)
C1
(Chip Carrier)
ORDER CODES :
HCC4724BF
H CF 4724 BM 1
HCF4724BEY
H CF 4724 BC 1
PIN CONNECTIONS
September 1988
1/14
1 page  
HCC/HCF4724B
DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25 oC, CL = 50 pF, RL = 200 KΩ,
typical temperature coefficent for all VDD values is 03 %/oC, all input rise and fall times= 20 ns)
Symbol
Parameter
tPLH Propagation Delay Time
tPHL Data to Output
tPLH Propagation Delay Time
tPHL Write Disable to Output
tPHL Propagation Delay Time
Reset to Output
tPLH Propagation Delay Time
tPHL Address to Output
tTLH Transition Time Any Output
tTHL
tW Minimum Pulse Width
Data
Minimum Pulse Width
Address
Minimum Pulse Width
Reset
ts Minimum Setup Time
Data to Write Disable
tH Minimum Holf Time
Data to Write Disable
CIN Input Capacitance
Test Conditions
VDD (V)
(See Figure 1) 5
10
15
(See Figure 1) 5
10
15
(See Figure 1) 5
10
15
(See Figure 1) 5
10
15
5
10
15
(See Figure 1) 5
10
15
(See Figure 1) 5
10
15
(See Figure 1) 5
10
15
(See Figure 1) 5
10
15
(See Figure 1) 5
10
15
Any
Input
Min.
Value
Typ.
200
75
50
200
80
60
175
80
65
225
100
75
100
50
40
100
50
40
200
100
65
75
40
25
50
25
20
75
40
25
5
Max.
400
150
100
400
160
120
350
160
130
450
200
150
200
100
80
200
100
80
400
200
125
150
75
50
100
50
35
150
75
50
7.5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
5/14
5 Page 
DIM.
A
B
D
E
e3
F
G
H
L
M
N
P
Q
HCC/HCF4724B
Ceramic DIP16/1 MECHANICAL DATA
MIN.
0.38
2.29
0.4
1.17
0.22
0.51
7.8
mm
TYP.
3.3
17.78
MAX.
20
7
2.79
0.55
1.52
0.31
1.27
10.3
8.05
5.08
MIN.
0.015
0.090
0.016
0.046
0.009
0.020
0.307
inch
TYP.
0.130
0.700
MAX.
0.787
0.276
0.110
0.022
0.060
0.012
0.050
0.406
0.317
0.200
P053D
11/14
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet HCF4724B.PDF ] | |
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