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PDF nRF24LU1 Data sheet ( Hoja de datos )
| Número de pieza | nRF24LU1 | |
| Descripción | Single Chip 2.4GHz Transceiver | |
| Fabricantes | Nordic | |
| Logotipo |  |
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nRF24LU1+
Single Chip 2.4 GHz Transceiver with USB
Microcontroller and Flash Memory
Product Specification v1.1
Key Features
Applications
• nRF24L01+ compatible RF transceiver
• Worldwide 2.4 GHz ISM band operation
• Up to 2 Mbps on air data rate
• Enhanced ShockBurst™ hardware link layer
• Air compatible with nRF24LU1, nRF24LE1,
nRF24L01+, nRF24L01, nRF2401A, nRF2402,
nRF24E1 and nRF24E2
• Low cost external ±60 ppm 16 MHz crystal
• Full speed USB 2.0 compliant device controller
• Up to 12 Mbps USB transfer rate
• 2 control, 10 bulk/interrupt and 2 ISO endpoints
• Dedicated 512 bytes endpoint buffer RAM
• Software controlled pull-up resistor for D+
• PLL for full-speed USB operation
• Voltage regulator, 4.0 to 5.25V supply range
• Enhanced 8-bit 8051 compatible
microcontroller
• Drop-in compatibility with nRF24LU1
• Reduced instruction cycle time
• 32-bit multiplication-division unit
• 16 or 32 kbytes of on-chip flash memory
• 2 kbytes of on-chip SRAM
• 6 general purpose digital input/output pins
• Hardware SPI slave and master, UART
• 3 16-bit timers/counters
• AES encryption/decryption co-processor
• Supports firmware upgrade over USB
• Supports FS2 hardware debugger
• Compact 32-pin 5x5mm QFN package
• Compact USB dongles for wireless
peripherals
• USB dongles for mouse, keyboards and
remotes
• USB dongle 3-in-1 desktop bundles
• USB dongle for advanced media center
remote controls
• USB dongle for game controllers
• Toys
All rights reserved.
Reproduction in whole or in part is prohibited without the prior written permission of the copyright holder.
April 2010
1 page  
nRF24LU1+ Product Specification
6.4.8
MultiCeiver™ ................................................................................... 43
6.4.9
Enhanced ShockBurst™ timing ....................................................... 45
6.4.10
Enhanced ShockBurst™ transaction diagram ................................. 48
6.4.11
Compatibility with ShockBurst™...................................................... 52
6.5 Data and control interface .................................................................... 53
6.5.1
SFR registers................................................................................... 53
6.5.2
SPI operation................................................................................... 54
6.5.3
Data FIFO........................................................................................ 55
6.5.4
Interrupt ........................................................................................... 56
6.6 Register map ........................................................................................ 57
6.6.1
Register map table .......................................................................... 57
7 USB Interface............................................................................................. 63
7.1 Features ............................................................................................... 63
7.2 Block diagram ...................................................................................... 64
7.3 Functional description .......................................................................... 65
7.4 Control endpoints ................................................................................. 69
7.4.1
Control endpoint 0 implementation .................................................. 69
7.4.2
Endpoint 0 registers ........................................................................ 69
7.4.3
Control transfer examples ............................................................... 70
7.5 Bulk/Interrupt endpoints ....................................................................... 72
7.5.1
Bulk/Interrupt endpoints implementation ......................................... 72
7.5.2
Bulk/Interrupt endpoints registers ................................................... 72
7.5.3
Bulk and interrupt endpoints initialization ........................................ 73
7.5.4
Data packet synchronization ........................................................... 74
7.5.5
Endpoint pairing............................................................................... 75
7.6 Isochronous endpoints ......................................................................... 75
7.6.1
Isochronous endpoints implementation ........................................... 75
7.6.2
Isochronous endpoints registers ..................................................... 76
7.6.3
ISO endpoints initialization .............................................................. 76
7.6.4
ISO transfers ................................................................................... 76
7.7 Memory configuration........................................................................... 77
7.7.1
On-chip memory map ...................................................................... 77
7.7.2
Setting ISO FIFO size..................................................................... 78
7.7.3
Setting Bulk OUT size ..................................................................... 79
7.7.4
Setting Bulk IN size ......................................................................... 79
7.8 The USB controller interrupts ............................................................... 80
7.8.1
Wakeup interrupt request ................................................................ 80
7.8.2
USB interrupt request ...................................................................... 80
7.8.3
USB interrupt vectors ...................................................................... 83
7.9 The USB controller registers ................................................................ 83
7.9.1
Bulk IN data buffers (inxbuf) ............................................................ 83
7.9.2
Bulk OUT data buffers (outxbuf) ...................................................... 84
7.9.3
Isochronous OUT endpoint data FIFO (out8dat) ............................. 84
7.9.4
Isochronous IN endpoint data FIFOs (in8dat) ................................ 84
7.9.5
Isochronous data bytes counter (out8bch/out8bcl) ......................... 84
7.9.6
Isochronous transfer error register (isoerr) ..................................... 84
Revision 1.1
Page 5 of 187
5 Page 
nRF24LU1+ Product Specification
1.3 Features
Features of the nRF24LU1+ include:
• Fast 8-bit MCU:
X Intel MCS 51 compliant instruction set
X Reduced instruction cycle time, up to 12x compared to legacy 8051
X 32 bit multiplication – division unit
• Memory:
X 16 or 32 kbytes of on-chip flash memory with security features
X 2 kbytes of on-chip RAM memory
X Pre-programmed USB bootloader in the on-chip flash memory.
• 6 programmable digital input/output pins configurable as:
X GPIO
X SPI master
X SPI slave
X External interrupts
X Timer inputs
X Full duplex serial port
X Debug interface
• High performance 2.4 GHz RF-transceiver
X True single chip GFSK transceiver
X Enhanced ShockBurst™ link layer support in HW:
X Packet assembly/disassembly
X Address and CRC computation
X Auto ACK and retransmit
X On the air data rate 250 kbps, 1 Mbps or 2 Mbps
X Digital interface (SPI) speed 0-8 Mbps
X 125 RF channel option, with 79 (2.402 GHz-2.480 GHz) channels within 2.400 - 2.4835 GHz
X Short switching time enable frequency hopping
X Fully RF compatible with nRF24LXX
X RF compatible with nRF2401A, nRF2402, nRF24E1, nRF24E2 in 250 kbps and 1 Mbps mode
• AES encryption/decryption HW-block with 128 bits key length
X ECB – Electronic Code Book mode
X CBC – Cipher Block Chaining
X CFB – Cipher FeedBack mode
X OFB – Output FeedBack mode
X CTR – Counter mode
• Full speed USB 2.0 compliant device controller supporting:
X Data transfer rates up to 12 Mbit/s
X Control, Interrupt, Bulk and ISO data transfer
X Endpoint 0 for control
X 5 input and 5 output Bulk/Interrupt endpoints
X 1 input and 1 output iso-synchronous endpoints
X Total 512 bytes of USB buffer endpoint memory sharable between endpoints
X On-chip USB transceiver PHY
X On-chip pull-up resistor on D+ line with software controlled disconnect
• Power management function:
X Low power design supporting fully static stop/ standby/ suspend modes
X Programmable MCU clock frequency from 64 kHz to 16 MHz
X On-chip voltage regulators supporting low power mode (supplied from USB power)
X Watchdog and wakeup functionality running in low power mode
Revision 1.1
Page 11 of 187
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet nRF24LU1.PDF ] | |
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