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PDF HCPL-0710 Data sheet ( Hoja de datos )
| Número de pieza | HCPL-0710 | |
| Descripción | 40 ns Prop. Delay/ SO-8 Optocoupler | |
| Fabricantes | Agilent(Hewlett-Packard) | |
| Logotipo | .gif "Agilent(Hewlett-Packard)"){kind=logo} |
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H
40 ns Prop. Delay,
SO-8 Optocoupler
Technical Data
HCPL-0710
Features
• +5 V CMOS Compatibility
• 8 ns max. Pulse Width
Distortion
• 20 ns max. Prop. Delay Skew
• High Speed: 12 Mbd
• 40 ns max. Prop. Delay
• 10 kV/µs Minimum Common
Mode Rejection
• 0°C to 85°C Temp. Range
• Safety and Regulatory
Approvals
UL Recognized
2500 V rms for 1 min. per
UL 1577
CSA Component Acceptance
Notice #5
Description
Available in the SO-8 package
style, the HCPL-0710 optocoupler
utilizes the latest CMOS IC
technology to achieve outstanding
performance with very low power
consumption. The HCPL-0710
requires only two bypass
capacitors for complete CMOS
compatability.
Basic building blocks of the
HCPL-0710 are a CMOS LED
driver IC, a high speed LED and a
CMOS detector IC. A CMOS logic
input signal controls the LED
driver IC which supplies current
to the LED. The detector IC
incorporates an integrated
photodiode, a high-speed
transimpedance amplifier, and a
voltage comparator with an
output driver.
Functional Diagram
**VDD1 1
8 VDD2**
Applications
• Digital Fieldbus Isolation:
DeviceNet, SDS, Profibus
• AC Plasma Display Panel
Level Shifting
• Multiplexed Data
Transmission
• Computer Peripheral
Interface
• Microprocessor System
Interface
VI 2
*3
GND1 4
LED1
SHIELD
7 NC*
IO
6 VO
5 GND2
TRUTH TABLE
(POSITIVE LOGIC)
VI, INPUT
H
L
LED1
OFF
ON
VO, OUTPUT
H
L
*Pin 3 is the anode of the internal LED and must be left unconnected for guaranteed data sheet performance.
Pin 7 is not connected internally. External connections to pin 7 are not recommended.
**A 0.1 µF bypass capacitor must be connected between pins 1 and 4, and 5 and 8.
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component
to prevent damage and/or degradation which may be induced by ESD.
1 page  
Package Characteristics
Parameter
Symbol
Input-Output Momentary
Withstand Voltage
Resistance
(Input-Output)
Capacitance
(Input-Output)
VISO
RI-O
CI-O
Input Capacitance
Input IC Junction-to-Case
Thermal Resistance
Output IC Junction-to-Case
Thermal Resistance
CI
θjci
θjco
Package Power Dissipation PPD
Min.
2500
Typ.
1012
0.6
3.0
160
135
Max.
150
Units
Vrms
Ω
pF
°C/W
mW
Test Conditions Fig.
RH ≤ 50%, t = 1 min.,
TA = 25°C
VI-O = 500 Vdc
f = 1 MHz
Thermocouple
located at center
underside of
package
Note
9, 10,
11
9
12
Notes:
1. Absolute Maximum ambient operating
temperature means the device will not
be damaged if operated under these
conditions. It does not guarantee
functionality.
2. The LED is ON when VI is low and OFF
when VI is high.
3. tPHL propagation delay is measured
from the 50% level on the falling edge
of the VI signal to the 50% level of the
falling edge of the VO signal. tPLH
propagation delay is measured from
the 50% level on the rising edge of the
VI signal to the 50% level of the rising
edge of the VO signal.
4. Mimimum Pulse Width is the shortest
pulse width at which 10% maximum,
Pulse Width Distortion can be guaran-
teed. Maximum Data Rate is the
inverse of Minimum Pulse Width.
Operating the HCPL-0710 at data rates
above 12.5 MBd is possible provided
PWD and data dependent jitter
increases and relaxed noise margins
5
0 °C
4 25 °C
85 °C
3
2
1
0
01 2 3 45
VI (V)
Figure 1. Typical Output Voltage vs.
Input Voltage.
are tolerable within the application.
For instance, if the maximum
allowable variation of bit width is 30%,
the maximum data rate becomes 37.5
MBd. Please note that HCPL-0710
performance above 12.5 MBd is not
guaranteed by Hewlett-Packard.
5. PWD is defined as |tPHL - tPLH|.
%PWD (percent pulse width distortion)
is equal to the PWD divided by pulse
width.
6. tPSK is equal to the magnitude of the
worst case difference in tPHL and/or
tPLH that will be seen between units at
any given temperature within the
recommended operating conditions.
7. CMH is the maximum common mode
voltage slew rate that can be sustained
while maintaining VO > 0.8 VDD2. CML
is the maximum common mode voltage
slew rate that can be sustained while
maintaining VO < 0.8 V. The common
mode voltage slew rates apply to both
rising and falling common mode
voltage edges.
2.2
0 °C
2.1 25 °C
85 °C
2.0
1.9
1.8
1.7
1.6
4.5
4.75 5 5.25
VDD1 (V)
5.5
Figure 2. Typical Input Voltage
Switching Threshold vs. Input Supply
Voltage.
8. Unloaded dynamic power dissipation is
calculated as follows: CPD * VDD2 * f +
IDD * VDD, where f is switching
frequency in MHz.
9. Device considered a two-terminal
device: pins 1, 2, 3, and 4 shorted
together and pins 5, 6, 7, and 8
shorted together.
10. In accordance with UL1577, each
optocoupler is proof tested by
applying an insulation test voltage
≥ 3000 VRMS for 1 second (leakage
detection current limit, II-O ≤ 5 µA).
11. The Input-Output Momentary With-
stand Voltage is a dielectric voltage
rating that should not be interpreted as
an input-output continuous voltage
rating. For the continuous voltage
rating refer to your equipment level
safety specification or HP Application
Note 1074 entitled “Optocoupler
Input-Output Endurance Voltage.”
12. CI is the capacitance measured at pin
2 (VI).
29
27
25
TPLH
23
21 TPHL
19
17
15
0 10 20 30 40 50 60 70 80
TA (C)
Figure 3. Typical Propagation Delays
vs. Temperature.
5 Page 
AC LINE
NODE/APP SPECIFIC
uP/CAN
HCPL
0710
HCPL
0710
TRANSCEIVER
LOCAL
NODE
SUPPLY
5 V REG.
GALVANIC
ISOLATION
BOUNDARY
DRAIN/SHIELD
SIGNAL
POWER
NETWORK
POWER
SUPPLY
Figure 17. Typical DeviceNet Node.
V+ (SIGNAL)
V– (SIGNAL)
V+ (POWER)
V– (POWER)
Implementing DeviceNet
and SDS with the
HCPL-0710
With transmission rates up to 1
Mbit/s, both DeviceNet and SDS
are based upon the same
broadcast-oriented, communica-
tions protocol — the Controller
Area Network (CAN). Three types
of isolated nodes are
recommended for use on these
networks: Isolated Node Powered
by the Network (Figure 18),
Isolated Node with Transceiver
Powered by the Network (Figure
19), and Isolated Node Providing
Power to the Network
(Figure 20).
Isolated Node Powered by the
Network
This type of node is very flexible
and as can be seen in Figure 18,
is regarded as “isolated” because
not all of its components have the
same ground reference. Yet, all
components are still powered by
the network. This node contains
two regulators: one is isolated and
powers the CAN controller, node-
specific application and isolated
(node) side of the two optocoup-
lers while the other is non-
isolated. The non-isolated
regulator supplies the transceiver
and the non-isolated (network)
half of the two optocouplers.
NODE/APP SPECIFIC
uP/CAN
HCPL
0710
HCPL
0710
TRANSCEIVER
REG.
ISOLATED
SWITCHING
POWER
SUPPLY
GALVANIC
ISOLATION
BOUNDARY
DRAIN/SHIELD
SIGNAL
POWER
NETWORK
POWER
SUPPLY
Figure 18. Isolated Node Powered by the Network.
V+ (SIGNAL)
V– (SIGNAL)
V+ (POWER)
V– (POWER)
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet HCPL-0710.PDF ] | |
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