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WPCT301 PDF даташит

Спецификация WPCT301 изготовлена ​​​​«Nuvoton» и имеет функцию, называемую «Trusted Platform Module (TPM)».

Детали детали

Номер произв WPCT301
Описание Trusted Platform Module (TPM)
Производители Nuvoton
логотип Nuvoton логотип 

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WPCT301 Даташит, Описание, Даташиты
 
March 2011
Revision 1.40
WPCT301/NPCT501 Trusted Platform Module (TPM) Version
1.2 with I2C Interface
General Description
The Nuvoton WPCT301/NPCT501 family of single-chip
Trusted Platform Modules (TPM) is a third-generation Nu-
voton SafeKeeperdevice that implements the TCG ver-
sion 1.2 specification for PC-Client TPM with the addition of
a serial data interface.
The WPCT301/NPCT501 is designed to reduce system
power-up time and Trusted OS loading time. It provides a
complete platform security solution for a wide range of com-
puter systems.
Features
General
Complete, single-chip TPM solution
No external parts required
Compatible with the Trusted Computing Group (TCG)
TPM 1.2 Main
Host Interface
TPM 1.2 Interface (TIS) emulation
Dedicated Interrupt signal
Secure General-Purpose I/O (GPIO)
Up to three GPIO pins
I/O pins individually configured as input or output
Configurable internal pull-up resistors
TCG 1.2-defined interface
Dedicated Physical Presence (PP) pin with config-
urable pull-up or pull-down resistor
Tick Counter
Bus Interface
I2C Bus Interface
I2C Slave
Up to 400 KHz clock operation (NPCT501)
Clocking and Supply
On-Chip Clock Generator
Power Supply
3.3V supply operation
Separate pins for main (VDD) and standby (VSB)
power supplies
Low standby power consumption
Package
28-pin Thin Shrink Small Outline Package (TSSOP28)
System Block Diagram
Host
© 2011 Nuvoton Technology Corporation
Physical
Presence
I2C Bus
WPCT301/
NPCT501
GPIO
www.nuvoton.com









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WPCT301 Даташит, Описание, Даташиты
Datasheet Revision Record
Revision Date
February 2008
March 2008
April 2008
June 2008
November 2009
January 2010
August 2010
December 2010
January 2011
March 2011
March 2011
Status
Comments
Revision 0.9 Preliminary Datasheet
Revision 1.0 Preliminary Datasheet, second release
Revision 1.01 Removed tWLB requirement
Fixed SPI_DO I/O definition in 1.3.1 Serial Interface
Fixed signal names in 3.4.3 I2C Timing and 3.4.4 SPI Timing diagrams
In 3.4.4 SPI Timing diagram, changed Max frequency of tSCK (SPI Timing) to
100 KHz
Revision 1.02 In 3.4.4 SPI Timing diagram, changed Max frequency of tSCK (SPI Timing) to
200 KHz
Replaced Figures 11 and 12 (page 20)
Revision 1.03 Nuvoton revision. Changed logos and company name.
Revision 1.04 Order numbers changed (...0WG to ...0WX)
Added description to SADD pin
Revision 1.05 Changed power-well to VDD for all pins in Section 1 (Signal/Pin Connection and
Description).
Changed SADD description in Section 1.3.3.
Changed Section 1.4 (Internal Pull-up and Pull-down Resistors).
Changed Section 4.4.2 (Reset Timing).
Updated Table 1 (“Buffer Types”) and updated Section 1.3 (“Signal/Pin
Description”) tables, accordingly.
Revision 1.10 Removed references to the Nuvoton WPCT300 (SPI Interface).
Added the NPCT501 device.
Revision 1.20 Typo fixes.
Added TPM Host Interface description (Section 3).
Revision 1.30 Changed tSRST max requirement from 2.5 s to none, in Power-Up Reset Timing
table (Section 4.4.2).
Added tRST.STA to I2C Timing table (Section 4.4.3).
Revision 1.40 Added NPCT501MA0WX order number to pinout diagram and back cover.
www.nuvoton.com
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Revision 1.40









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WPCT301 Даташит, Описание, Даташиты
Table of Contents
1.0 Signal/Pin Connection and Description
1.1 CONNECTION DIAGRAM ........................................................................................................... 4
1.2 BUFFER TYPES AND SIGNAL/PIN DIRECTORY ...................................................................... 4
1.3 SIGNAL/PIN DESCRIPTIONS ..................................................................................................... 5
1.3.1 Serial Interface .............................................................................................................. 5
1.3.2 Inputs and Outputs ....................................................................................................... 5
1.3.3 Configuration Straps and Testing .................................................................................. 5
1.3.4 Power and Ground ........................................................................................................ 5
1.3.5 Reserved ....................................................................................................................... 6
1.4 INTERNAL PULL-UP AND PULL-DOWN RESISTORS .............................................................. 6
2.0 Trusted Platform Module (TPM) Overview
2.1 SYSTEM CONNECTIONS .......................................................................................................... 7
2.2 POWER MANAGEMENT (PM) .................................................................................................... 7
2.3 HOST INTERFACE ..................................................................................................................... 7
2.4 RESET ......................................................................................................................................... 7
3.0 TPM Host Interface
3.1 SERIAL TPM INTERFACE PROTOCOL (TSIP) ......................................................................... 8
3.1.1 State Machine, Flow and Timeouts ............................................................................... 8
3.1.2 TIS Register Mapping .................................................................................................... 9
4.0 Device Specifications
4.1 GENERAL DC ELECTRICAL CHARACTERISTICS ................................................................. 10
4.1.1 Recommended Operating Conditions ......................................................................... 10
4.1.2 Absolute Maximum Ratings ......................................................................................... 10
4.1.3 Capacitance ................................................................................................................ 10
4.1.4 Power Consumption under Recommended Operating Conditions .............................. 11
4.2 DC CHARACTERISTICS OF PINS BY I/O BUFFER TYPES ................................................... 12
4.2.1 Input, TTL Compatible, with Schmitt Trigger ............................................................... 12
4.2.2 Input, Reset Pin ........................................................................................................... 12
4.2.3 Output, TTL/CMOS Compatible, Push-Pull Buffer ...................................................... 12
4.2.4 Output, Open Drain Buffer ........................................................................................... 13
4.2.5 Notes and Exceptions .................................................................................................. 13
4.3 INTERNAL RESISTORS ........................................................................................................... 14
4.3.1 Pull-Up Resistor ........................................................................................................... 15
4.3.2 Pull-Down Resistor ...................................................................................................... 15
4.4 AC ELECTRICAL CHARACTERISTICS .................................................................................... 16
4.4.1 AC Test Conditions ................................................................................................... 16
4.4.2 Reset Timing ............................................................................................................... 17
Power-Up Reset ................................................................................................... 17
4.4.3 I2C Timing .................................................................................................................... 18
4.5 PACKAGE THERMAL INFORMATION ..................................................................................... 20
Revision 1.40
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