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PDF HCS112KMSR Data sheet ( Hoja de datos )

Número de pieza HCS112KMSR
Descripción Radiation Hardened Dual JK Flip-Flop
Fabricantes Intersil Corporation　
Logotipo Intersil Corporation Logotipo



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No Preview Available ! HCS112KMSR Hoja de datos, Descripción, Manual

HCS112MS
September 1995
Radiation Hardened
Dual JK Flip-Flop
Features
Pinouts
• 3 Micron Radiation Hardened SOS CMOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm2/mg
• Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/
Bit-Day (Typ)
• Dose Rate Survivability: >1 x 1012 RAD (Si)/s
• Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse
• Latch-Up Free Under Any Conditions
• Military Temperature Range: -55oC to +125oC
• Significant Power Reduction Compared to LSTTL ICs
16 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T16, LEAD FINISH C
TOP VIEW
CP1 1
KA 2
JA 3
SA 4
QA 5
QA 6
QB 7
GND 8
16 VCC
15 RA
14 RB
13 CPB
12 KB
11 JB
10 SB
9 QB
• DC Operating Voltage Range: 4.5V to 5.5V
• Input Logic Levels
- VIL = 30% of VCC Max
- VIH = 70% of VCC Min
• Input Current Levels Ii ≤ 5µA at VOL, VOH
Description
The Intersil HCS112MS is a Radiation Hardened dual JK
flip-flop with set and reset. The output changes state on the
negative going transition of the clock pulse. Set and reset
are accomplished asynchronously by a logic low input level.
The HCS112MS utilizes advanced CMOS/SOS technology
to achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
16 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
MIL-STD-1835 CDFP4-F16, LEAD FINISH C
TOP VIEW
CP1
KA
JA
SA
QA
QA
QB
GND
1 16
2 15
3 14
4 13
5 12
6 11
7 10
89
VCC
RA
RB
CPB
KB
JB
SB
QB
The HCS112MS is supplied in a 16 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
Ordering Information
PART NUMBER
HCS112DMSR
HCS112KMSR
HCS112D/Sample
HCS112K/Sample
HCS112HMSR
TEMPERATURE RANGE
-55oC to +125oC
-55oC to +125oC
+25oC
+25oC
+25oC
SCREENING LEVEL
Intersil Class S Equivalent
Intersil Class S Equivalent
Sample
Sample
Die
PACKAGE
16 Lead SBDIP
16 Lead Ceramic Flatpack
16 Lead SBDIP
16 Lead Ceramic Flatpack
Die
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
11
Spec Number 518830
File Number 3558.1

1 page




HCS112KMSR pdf
Specifications HCS112MS
TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
Supply Current
Output Current (Sink)
Output Current
(Source)
Output Voltage Low
Output Voltage High
Input Leakage Current
Noise Immunity
Functional Test
SYMBOL
(NOTES 1, 2)
CONDITIONS
ICC VCC = 5.5V, VIN = VCC or GND
IOL VCC = VIH = 4.5V, VIL = 0.0V,
VOUT = 0.4V
IOH VCC = VIH = 4.5V, VIL = 0.0V,
VOUT = VCC -0.4V
VOL
VCC = 5.5V, VIH = 3.85V,
VIL = 1.65V, IOL = 50µA
VCC = 4.5V, VIH = 3.15V,
VIL = 1.35V, IOL = 50µA
VOH
VCC = 5.5V, VIH = 3.85V,
VIL =1.65V, IOH = -50µA
VCC = 4.5V, VIH = 3.15V,
VIL =1.35V, IOH = -50µA
IIN VCC = 5.5V, VIN = VCC or GND
FN VCC = 4.5V, VIH =3.15V, VIL = 1.35V,
(Note 3)
TEMPERATURE
+25oC
+25oC
200K LIMITS
RAD
MIN MAX UNITS
- 0.4 mA
4.0 - mA
+25oC
-4.0 - mA
+25oC
- 0.1 V
+25oC
- 0.1 V
+25oC
+25oC
+25oC
+25oC
VCC
-0.1
VCC
-0.1
-
-
-
±5
-
V
V
µA
-
PROPAGATION DELAY
CP to Q, Q
S to Q
S to Q
R to Q
R to Q
TPHL,
TPLH
TPLH
TPHL
TPHL
TPLH
VCC = 4.5V
VCC = 4.5V
VCC = 4.5V
VCC = 4.5V
VCC = 4.5V
+25oC
+25oC
+25oC
+25oC
+25oC
2 35 ns
2 33 ns
2 33 ns
2 32 ns
2 32 ns
NOTES:
1. All voltages referenced to device GND.
2. AC measurements assume RL = 500Ω, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = 3V.
3. For functional tests VO ≥ 4.0V is recognized as a logic “1”, and VO ≤ 0.5V is recognized as a logic “0”.
TABLE 5. BURN-IN AND OPERATING LIFE TEST, DELTA PARAMETERS (+25oC)
PARAMETER
GROUP B
SUBGROUP
DELTA LIMIT
ICC 5 6µA
IOL/IOH
5 -15% of 0 Hour
Spec Number 518830
15

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