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PDF HCS11MS Data sheet ( Hoja de datos )
| Número de pieza | HCS11MS | |
| Descripción | Radiation Hardened Triple 3-Input AND Gate | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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HCS11MS
November 1994
Radiation Hardened
Triple 3-Input AND Gate
Features
Pinouts
• 3 Micron Radiation Hardened SOS CMOS
• Total Dose 200K or 1 Mega-RAD(Si)
• Dose Rate Upset >1010 RAD(Si)/s 20ns Pulse
• Cosmic Ray Upset Immunity < 2 x 10-9 Errors/Gate Day
(Typ)
• Latch-Up Free Under Any Conditions
• Military Temperature Range: -55oC to +125oC
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• Input Logic Levels
- VIL = 30% of VCC Max
- VIH = 70% of VCC Min
• Input Current Levels Ii ≤ 5µA at VOL, VOH
14 PIN CERAMIC DUAL-IN-LINE
MIL-STD-1835 DESIGNATOR CDIP2-T14, LEAD FINISH C
TOP VIEW
A1 1
B1 2
A2 3
B2 4
C2 5
Y2 6
GND 7
14 VCC
13 C1
12 Y1
11 C3
10 B3
9 A3
8 Y3
Description
The Intersil HCS11MS is a Radiation Hardened Triple 3-
Input AND Gate. A high on all inputs forces the output to a
High state.
The HCS11MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCS11MS is supplied in a 14 lead Weld Seal Ceramic
flatpack (K suffix) or a Weld Seal Ceramic Dual-In-Line
Package (D suffix).
14 PIN CERAMIC FLAT PACK
MIL-STD-1835 DESIGNATOR CDFP3-F14, LEAD FINISH C
TOP VIEW
A1
B1
A2
B2
C2
Y2
GND
1 14
2 13
3 12
4 11
5 10
69
78
VCC
C1
Y1
C3
B3
A3
Y3
Truth Table
INPUTS
OUTPUTS
An Bn Cn
Yn
LLL
L
L LH
L
LHL
L
L HH
L
HL L
L
HLH
L
HH L
L
HHH
H
NOTE: L = Logic Level Low, H = Logic level High
Functional Diagram
(1, 3, 9)
An
(2, 4, 10)
Bn
(13, 5, 11)
Cn
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-135
(12, 6, 8)
Yn
File Number 3048
1 page  
Specifications HCS11MS
TABLE 8. STATIC AND DYNAMIC BURN-IN TEST CONNECTIONS
OPEN
GROUND
1/2 VCC = 3V ± 0.5V
6, 8, 12
1, 2, 3, 4, 5, 7, 9, 10, 11,
13
-
STATIC BURN-IN II TEST CONNECTIONS (Note 1)
6, 8, 12
7
-
DYNAMIC BURN-IN I TEST CONNECTIONS (Note 2)
- 7 6, 8, 12
VCC = 6V ± 0.5V
14
1, 2, 3, 4, 5, 9, 10,
11, 13, 14
14
NOTES:
1. Each pin except VCC and GND will have a resistor of 10KΩ ± 5% for static burn-in.
2. Each pin except VCC and GND will have a resistor of 680KΩ ± 5% for dynamic burn-in.
OSCILLATOR
50kHz
25kHz
--
--
1, 2, 3, 4, 5, 9,
10, 11, 13
-
OPEN
6, 8, 12
TABLE 9. IRRADIATION TEST CONNECTIONS
GROUND
7
VCC = 5V ± 0.5V
1, 2, 3, 4, 5, 9, 10, 11, 13, 14
AC Timing Diagrams
VIH
VIL
VOH
VOL
VOH
VOL
VS INPUT
TPLH
VS
TPHL
OUTPUT
TTLH
20%
80% 80%
OUTPUT
TTHL
20%
AC VOLTAGE LEVELS
PARAMETER
HCS
VCC
4.50
VIH 4.50
VS 2.25
VIL 0
GND
0
UNITS
V
V
V
V
V
AC Load Circuit
DUT
CL
CL = 50pF
RL = 500Ω
TEST
POINT
RL
7-139
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet HCS11MS.PDF ] | |
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