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PDF HCS410-IST Data sheet ( Hoja de datos )
| Número de pieza | HCS410-IST | |
| Descripción | KEELOQ CODE HOPPING ENCODER AND TRANSPONDER | |
| Fabricantes | Microchip Technology | |
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M
HCS410
Code Hopping Encoder and Transponder*
FEATURES
PACKAGE TYPES
Security
• Two programmable 64-bit encoder keys
• 16/32-bit bi-directional challenge and response
using one of two keys
• 69-bit transmission length
• 32-bit unidirectional code hopping, 37-bit
nonencrypted portion
• Encoder keys are read protected
• Programmable 28/32-bit serial number
• 60/64-bit, read-protected seed for secure learning
• Three IFF encryption algorithms
• Delayed increment mechanism
• Asynchronous transponder communication
• Queuing information transmitted
Operating
• 2.0V to 6.6V operation, 13V encoder only
operation
• Three switch inputs [S2, S1, S0]—seven functions
• Batteryless bi-directional transponder
• Selectable baud rate and code word blanking
• Automatic code word completion
• Battery low signal transmitted
• Nonvolatile synchronization
• PWM or Manchester RF encoding
• Combined transmitter, transponder operation
• Anti-collision of multiple transponders
• Passive proximity activation
• Device protected against reverse battery
• Intelligent damping for high Q LC-circuits
Other
• 37-bit nonencrypted part contains 28/32-bit serial
number, 4/0-bit function code, 1-bit battery low,
2-bit CRC, 2-bit queue
• Simple programming interface
• On-chip tunable RC oscillator (±10%)
• On-chip EEPROM
• 64-bit user EEPROM in transponder mode
• Battery-low LED indication
• SQTP serialization quick-time programming
• 8-pin PDIP/SOIC/TSSOP and die
PDIP, SOIC
S0 1
S1 2
S2/LED 3
LC1 4
8 VDD
7 LC0
6 PWM
5 GND
TSSOP
S2/LED
LC1
GND
PWM
1
2
3
4
8 S1
7 S0
6 VDD
5 LC0
BLOCK DIAGRAM
VDD Power
Control
Oscillator
Configuration Register
S0
Debounce
Address
Decoding
EEPROM
S1 Wakeup Control
Logic
and
Queuer
S2 LED
Control
LCI0
LCI1
PWM
PWM
Driver
PPM
Detector
PWM
PPM
Manch.
Encoder
Typical Applications
• Automotive remote entry systems
• Automotive alarm systems
• Automotive immobilizers
• Gate and garage openers
• Electronic door locks (Home/Office/Hotel)
• Burglar alarm systems
• Proximity access control
KEELOQ is a registered trademark of Microchip Technology Inc.
*Code hopping encoder patents issued in Europe, U.S.A., R.S.A.—U.S.A.: 5,517,187; Europe: 0459781
© 1997 Microchip Technology Inc.
Preliminary
DS40158C-page 1
1 page  
HCS410
1.3 KEELOQ IFF
The HCS410 can be used as an IFF transponder for
verification of a token. In IFF mode the HCS410 is ide-
ally suited for authentication of a key before disarming
a vehicle immobilizer. Once the key has been inserted
in the car’s ignition the decoder would inductively poll
the key validating it before disarming the immobilizer.
IFF validation of the token involves a random challenge
being sent by a decoder to a token. The token then gen-
erates a response to the challenge and sends this
response to the decoder (Figure 1-2). The decoder cal-
culates an expected response using the same chal-
lenge. The expected response is compared to the
response received from the token. If the responses
match, the token is identified as a valid token and the
decoder can take appropriate action.
The HCS410 can do either 16 or 32-bit IFF. The
HCS410 has two encryption algorithms that can be
used to generate a response to a challenge. In addition
there are up to two encoder keys that can be used by
the HCS410. Typically each HCS410 will be pro-
grammed with a unique encoder key(s).
In IFF mode, the HCS410 will wait for a command from
the base station and respond to the command. The
command can either request a read/write from user
EEPROM or an IFF challenge response. A given 16 or
32-bit challenge will produce a unique 16/32-bit
response, based on the IFF key and IFF algorithm
used.
FIGURE 1-2: IBASIC OPERATION OF AN IFF TOKEN
Challenge Received from Decoder
EEPROM Array
IFF Key
Serial Number
KEELOQ
IFF
Algorithm
Read by Decoder
Serial Number Response
© 1997 Microchip Technology Inc.
Preliminary
DS40158C-page 5
5 Page 
HCS410
2.3 Code Hopping Mode Special Features
2.3.1 CODE WORD COMPLETION
Code word completion is an automatic feature that
ensures that the entire code word is transmitted, even
if the button is released before the transmission is com-
plete. The HCS410 encoder powers itself up when a
button is pushed and powers itself down after the com-
mand is finished (Figure 2-7). If MTX3 is set in the con-
figuration word, a minimum of three transmissions will
be transmitted when the HCS410 is activated, even if
the buttons are released.
If less than seven words have been transmitted when
the buttons are released, the HCS410 will complete the
current word. If more than seven words have been
transmitted, and the button is released, the PWM out-
put is immediately switched off.
2.3.2 CODE WORD BLANKING ENABLE
Federal Communications Commission (FCC) part 15
rules specify the limits on fundamental power and
harmonics that can be transmitted. Power is calculated
on the worst case average power transmitted in a
100ms window. It is therefore advantageous to
minimize the duty cycle of the transmitted word. This
can be achieved by minimizing the duty cycle of the
individual bits and by blanking out consecutive words.
Code Word Blanking Enable (CWBE) is used for
reducing the average power of a transmission
(Figure 2-12). Using the CWBE allows the user to
transmit a higher amplitude transmission if the
transmission length is shorter. The FCC puts
FIGURE 2-12: CODE WORD BLANKING ENABLE
Amplitude
CWBE Disabled
(All words transmitted)
CWBE Enabled
(1 out of 2 transmitted)
A
2A
constraints on the average power that can be
transmitted by a device, and CWBE effectively prevents
continuous transmission by only allowing the transmis-
sion of every second or fourth word. This reduces the
average power transmitted and hence, assists in FCC
approval of a transmitter device.
The HCS410 will either transmit all code words, 1 in 2
or 1 in 4 code words, depending on the baud rate
selected and the code word blanking option. See
Section 3.7 for additional details.
2.3.3 CRC (CYCLE REDUNDANCY CHECK) BITS
The CRC bits are calculated on the 65 previously trans-
mitted bits. The CRC bits can be used by the receiver
to check the data integrity before processing starts. The
CRC can detect all single bit and 66% of double bit
errors. The CRC is computed as follows:
EQUATION 2-1: CRC CALCULATION
CRC[1]n + 1 = CRC[0]n ⊕ Din
and
CRC[0]n + 1 = (CRC[0]n ⊕ Din) ⊕ CRC[1]n
with
CRC[1, 0]0 = 0
and Din the nth transmission bit 0 ≤ n ≤ 64
One Code Word
CWBE Enabled
(1 out of 4 transmitted)
4A
Time
© 1997 Microchip Technology Inc.
Preliminary
DS40158C-page 11
11 Page | ||
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