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HCS573DMSR PDF даташит

Спецификация HCS573DMSR изготовлена ​​​​«Intersil Corporation» и имеет функцию, называемую «Radiation Hardened Octal Transparent Latch/ Three-State».

Детали детали

Номер произв HCS573DMSR
Описание Radiation Hardened Octal Transparent Latch/ Three-State
Производители Intersil Corporation
логотип Intersil Corporation логотип 

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HCS573DMSR Даташит, Описание, Даташиты
HCS573MS
September 1995
Radiation Hardened
Octal Transparent Latch, Three-State
Features
• 3 Micron Radiation Hardened SOS CMOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm2/mg
• Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-
Day (Typ)
• Dose Rate Survivability: >1 x 1012 RAD (Si)/s
• Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse
• Latch-Up Free Under Any Conditions
• Fanout (Over Temperature Range)
- Bus Driver Outputs - 15 LSTTL Loads
• Military Temperature Range: -55oC to +125oC
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• Input Logic Levels
- VIL = 0.3 VCC Max
- VIH = 0.7 VCC Min
• Input Current Levels Ii 5µA at VOL, VOH
Description
The Intersil HCS573MS is a Radiation Hardened octal transpar-
ent three-state latch with an active low output enable. The
HCS573MS utilizes advanced CMOS/SOS technology. The
outputs are transparent to the inputs when the Latch Enable (LE)
is HIGH. When the Latch Enable (LE) goes LOW, the data is
latched. The Output Enable (OE) controls the tri-state outputs.
When the Output Enable (OE) is HIGH, the outputs are in the
high impedance state. The latch operation is independent of the
state of the Output Enable.
The HCS573MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCS573MS is supplied in a 20 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
Pinouts
20 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T20, LEAD FINISH C
TOP VIEW
OE 1
D0 2
D1 3
D2 4
D3 5
D4 6
D5 7
D6 8
D7 9
GND 10
20 VCC
19 Q0
18 Q1
17 Q2
16 Q3
15 Q4
14 Q5
13 Q6
12 Q7
11 LE
20 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
MIL-STD-1835 CDFP4-F20, LEAD FINISH C
TOP VIEW
OE
D0
D1
D2
D3
D4
D5
D6
D7
GND
1 20
2 19
3 18
4 17
5 16
6 15
7 14
8 13
9 12
10 11
VCC
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
LE
Ordering Information
PART NUMBER
HCS573DMSR
HCS573KMSR
HCS573D/Sample
HCS573K/Sample
HCS573HMSR
TEMPERATURE RANGE
-55oC to +125oC
-55oC to +125oC
+25oC
+25oC
+25oC
SCREENING LEVEL
Intersil Class S Equivalent
Intersil Class S Equivalent
Sample
Sample
Die
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
324
PACKAGE
20 Lead SBDIP
20 Lead Ceramic Flatpack
20 Lead SBDIP
20 Lead Ceramic Flatpack
Die
Spec Number 518771
File Number 4056









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HCS573DMSR Даташит, Описание, Даташиты
Functional Diagram
HCS573MS
PP
OE OE
LE
A
LE LE
NP
LE
Dn
P
N
LE
LE
P
N
LE
N
A
OE
Qn
OE
N
TRUTH TABLE
OUTPUT ENABLE
LATCH ENABLE
DATA
L HH
L HL
L LI
L Lh
H XX
H = High Level
L = Low Level
X = Immaterial
Z = High Impedance
I = Low voltage level prior to the high-to-low latch enable transition
h = High voltage level prior to the high-to-low latch enable transition
OUTPUT
H
L
L
H
Z
P
Qn
N
Spec Number 518771
325









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HCS573DMSR Даташит, Описание, Даташиты
Specifications HCS573MS
Absolute Maximum Ratings
Reliability Information
Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VCC +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
DC Drain Current, Any One Output. . . . . . . . . . . . . . . . . . . . . . .±25mA
(All Voltage Reference to the VSS Terminal)
Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC
Lead Temperature (Soldering 10sec) . . . . . . . . . . . . . . . . . . +265oC
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Resistance
θJA θJC
SBDIP Package. . . . . . . . . . . . . . . . . . . . 72oC/W 24oC/W
Ceramic Flatpack Package . . . . . . . . . . . 107oC/W 28oC/W
Maximum Package Power Dissipation at +125oC Ambient
SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.69W
Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 0.47W
If device power exceeds package dissipation capability, provide heat
sinking or derate linearly at the following rate:
SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.9mW/oC
Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . 9.3mW/oC
CAUTION: As with all semiconductors, stress listed under “Absolute Maximum Ratings” may be applied to devices (one at a time) without resulting in permanent
damage. This is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The conditions listed
under “Electrical Performance Characteristics” are the only conditions recommended for satisfactory device operation..
Operating Conditions
Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Input Rise and Fall Times at VCC = 4.5V (TR, TF) . . . . .500ns Max
Operating Temperature Range (TA) . . . . . . . . . . . . -55oC to +125oC
Input Low Voltage (VIL). . . . . . . . . . . . . . . . . . . 0.0V to 30% of VCC
Input High Voltage (VIH) . . . . . . . . . . . . . . . . . . 70% of VCC to VCC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
Quiescent Current
SYMBOL
(NOTE 1)
CONDITIONS
ICC VCC = 5.5V,
VIN = VCC or GND
Output Current
(Sink)
IOL VCC = 4.5V, VIH = 4.5V,
VOUT = 0.4V, VIL = 0V
Output Current
(Source)
Output Voltage Low
Output Voltage High
Input Leakage
Current
IOH
VOL
VOH
IIN
VCC = 4.5V, VIH = 4.5V,
VOUT = VCC -0.4V,
VIL = 0V
VCC = 4.5V, VIH = 3.15V,
IOL = 50µA, VIL = 1.35V
VCC = 5.5V, VIH = 3.85V,
IOL = 50µA, VIL = 1.65V
VCC = 4.5V, VIH = 3.15V,
IOH = -50µA, VIL = 1.35V
VCC = 5.5V, VIH = 3.85V,
IOH = -50µA, VIL = 1.65V
VCC = 5.5V, VIN = VCC or
GND
Output Leakage
Current
IOZ VCC = 5.5V, VIN = 0V or
VCC
Noise Immunity
Functional Test
FN VCC = 4.5V,
VIH = 0.70(VCC),
VIL = 0.30(VCC) (Note 2)
GROUP
A SUB-
GROUPS
1
2, 3
1
2, 3
1
2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1
2, 3
1
2, 3
7, 8A, 8B
TEMPERATURE
+25oC
+125oC, -55oC
+25oC
+125oC, -55oC
+25oC
+125oC, -55oC
+25oC, +125oC, -55oC
+25oC, +125oC, -55oC
+25oC, +125oC, -55oC
+25oC, +125oC, -55oC
+25oC
+125oC, -55oC
+25oC
+125oC, -55oC
+25oC, +125oC, -55oC
NOTES:
1. All voltages reference to device GND.
2. For functional tests VO 4.0V is recognized as a logic “1”, and VO 0.5V is recognized as a logic “0”.
LIMITS
MIN MAX UNITS
- 40 µA
- 750 µA
7.2 - mA
6.0 - mA
-7.2 - mA
-6.0 - mA
- 0.1 V
- 0.1 V
VCC
-0.1
VCC
-0.1
-
-
-
-
-
-
-
±0.5
±5.0
±1.0
±50
-
V
V
µA
µA
µA
µA
-
Spec Number 518771
326










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Номер в каталогеОписаниеПроизводители
HCS573DMSRRadiation Hardened Octal Transparent Latch/ Three-StateIntersil Corporation
Intersil Corporation

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