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PDF HCS86MS Data sheet ( Hoja de datos )
| Número de pieza | HCS86MS | |
| Descripción | Radiation Hardened Quad 2-Input Exclusive OR Gate | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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HCS86MS
September 1995
Radiation Hardened
Quad 2-Input Exclusive OR Gate
Features
Pinouts
• 3 Micron Radiation Hardened SOS CMOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm2/mg
• Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day
(Typ)
• Dose Rate Survivability: >1 x 1012 RAD (Si)/s
• Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse
• Latch-Up Free Under Any Conditions
• Military Temperature Range: -55oC to +125oC
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• Input Logic Levels
- VIL = 30% of VCC Max
- VIH = 70% of VCC Min
• Input Current Levels Ii ≤ 5µA at VOL, VOH
14 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-183S CDIP2-T14, LEAD FINISH C
TOP VIEW
A1 1
B1 2
Y1 3
A2 4
B2 5
Y2 6
GND 7
14 VCC
13 B4
12 A4
11 Y4
10 B3
9 A3
8 Y3
14 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
MIL-STD-183S CDFP3-F14, LEAD FINISH C
TOP VIEW
Description
The Intersil HCS86MS is a Radiation Hardened Quad 2-Input
Exclusive OR Gate. A high on any one input exclusively will
change the output to a High state.
The HCS86MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family with
either TTL or CMOS input compatibility.
A1
B1
Y1
A2
B2
Y2
GND
1 14
2 13
3 12
4 11
5 10
69
78
VCC
B4
A4
Y4
B3
A3
Y3
The HCS86MS is supplied in a 14 lead Weld Seal Ceramic
flatpack (K suffix) or a Weld Seal Ceramic Dual-In-Line Package
(D suffix).
Ordering Information
PART
NUMBER
HCS86DMSR
HCS86KMSR
HCS86D/
Sample
HCS86K/
Sample
HCS86HMSR
TEMPERATURE
RANGE
-55oC to +125oC
-55oC to +125oC
+25oC
SCREENING
LEVEL
Intersil Class
S Equivalent
Intersil Class
S Equivalent
Sample
PACKAGE
14 Lead SBDIP
14 Lead Ceramic
Flatpack
14 Lead SBDIP
+25oC
+25oC
Sample
Die
14 Lead Ceramic
Flatpack
Die
Functional Diagram
(1, 4, 9, 12)
An
Bn
(2, 5, 10, 13)
(3, 6, 8, 11)
Yn
TRUTH TABLE
INPUTS
OUTPUTS
An Bn Yn
LLL
L HH
HLH
HH L
NOTE: L = Logic Level Low, H = Logic level High
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
93
Spec Number 518773
File Number 3058.1
1 page  
Specifications HCS86MS
TABLE 8. STATIC AND DYNAMIC BURN-IN TEST CONNECTIONS
OSCILLATOR
OPEN
GROUND
1/2 VCC = 3V ± 0.5V VCC = 6V ± 0.5V
50kHz
25kHz
STATIC BURN-IN I TEST CONDITIONS (Note 1)
3, 6, 8, 11
1, 2, 4, 5, 7, 9, 10, 12,
13
-
14 - -
STATIC BURN-IN II TEST CONNECTIONS (Note 1)
3, 6, 8, 11
7
-
1, 2, 4, 5, 9, 10, 12,
-
13, 14
-
DYNAMIC BURN-IN I TEST CONNECTIONS (Note 2)
-
7
3, 6, 8, 11
14
1, 2, 4, 5, 9, 10,
-
12, 13
NOTES:
1. Each pin except VCC and GND will have a resistor of 10KΩ ± 5% for static burn-in.
2. Each pin except VCC and GND will have a resistor of 1KΩ ± 5% for dynamic burn-in.
TABLE 9. IRRADIATION TEST CONNECTIONS
OPEN
GROUND
VCC = 5V ± 0.5V
3, 6, 8, 11 7 1, 2, 4, 5, 9, 10, 12, 13, 14
NOTE: Each pin except VCC and GND will have a resistor of 47KΩ ± 5% for irradiation testing.
Group E, Subgroup 2, sample size is 4 dice/wafer 0 failures.
Spec Number 518773
97
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet HCS86MS.PDF ] | |
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