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PDF HCTS112DMSR Data sheet ( Hoja de datos )

Número de pieza HCTS112DMSR
Descripción Radiation Hardened Dual JK Flip-Flop
Fabricantes Intersil Corporation　
Logotipo Intersil Corporation Logotipo



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HCTS112MS
September 1995
Radiation Hardened
Dual JK Flip-Flop
Features
Pinouts
• 3 Micron Radiation Hardened SOS CMOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm2/mg
• Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/
Bit-Day (Typ)
• Dose Rate Survivability: >1 x 1012 RAD (Si)/s
• Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse
• Cosmic Ray Upset Rate 2 x 10-9 Errors/Bit Day (Typ)
• Latch-Up Free Under Any Conditions
• Military Temperature Range: -55oC to +125oC
16 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T16
TOP VIEW
CP1 1
K1 2
J1 3
S1 4
Q1 5
Q1 6
Q2 7
GND 8
16 VCC
15 R1
14 R2
13 CP2
12 K2
11 J2
10 S2
9 Q2
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• LSTTL Input Compatibility
- VIL = 0.8V Max
- VIH = VCC/2 Min
• Input Current Levels Ii ≤ 5µA at VOL, VOH
Description
The Intersil HCTS112MS is a Radiation Hardened dual JK
flip-flop with set and reset. The flip-flop changes states with
the negative transition of the clock (CP1N or CP2N).
The HCTS112MS utilizes advanced CMOS/SOS technology
to achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
CP1
K1
J1
S1
Q1
Q1
Q2
GND
16 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
MIL-STD-1835 CDFP4-F16
TOP VIEW
1 16
2 15
3 14
4 13
5 12
6 11
7 10
89
The HCTS112MS is supplied in a 16 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
VCC
R1
R2
CP2
K2
J2
S2
Q2
Ordering Information
PART NUMBER
HCTS112DMSR
HCTS112KMSR
HCTS112D/Sample
HCTS112K/Sample
HCTS112HMSR
TEMPERATURE RANGE
-55oC to +125oC
-55oC to +125oC
+25oC
+25oC
+25oC
SCREENING LEVEL
Intersil Class S Equivalent
Intersil Class S Equivalent
Sample
Sample
Die
PACKAGE
16 Lead SBDIP
16 Lead Ceramic Flatpack
16 Lead SBDIP
16 Lead Ceramic Flatpack
Die
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
490
Spec Number 518603
File Number 2467.2

1 page




HCTS112DMSR pdf
Specifications HCTS112MS
TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
Quiescent Current
Output Current (Sink)
Output Current
(Source)
Output Voltage Low
Output Voltage High
Input Leakage Current
Noise Immunity
Functional Test
CP to Q, Q
S to Q
S to Q
R to Q
R to Q
SYMBOL
(NOTES 1, 2)
CONDITIONS
ICC VCC = 5.5V, VIN = VCC or GND
IOL VCC = 4.5V, VIN = VCC or GND,
VOUT = 0.4V
IOH VCC = 4.5V, VIN = VCC or GND,
VOUT = VCC -0.4V
VOL
VCC = 4.5V or 5.5V, VIH = VCC/2,
VIL = 0.8V, IOL = 50µA
VOH
VCC = 4.5V or 5.5V, VIH = VCC/2,
VIL = 0.8V, IOH = -50µA
IIN VCC = 5.5V, VIN = VCC or GND
FN VCC = 4.5V, VIH = 2.25V, VIL = 0.8V,
(Note 3)
TPHL VCC = 4.5V
TPLH VCC = 4.5V
TPLH VCC = 4.5V
TPHL VCC = 4.5V
TPHL VCC = 4.5V
TPLH VCC = 4.5V
TEMPERATURE
+25oC
+25oC
200K LIMITS
RAD
MIN MAX UNITS
- 0.4 mA
4.0 - mA
+25oC
-4.0 - mA
+25oC
- 0.1 V
+25oC
+25oC
+25oC
VCC
-0.1
-
-
±5
-
V
µA
-
+25oC
+25oC
+25oC
+25oC
+25oC
+25oC
2 42 ns
2 38 ns
2 24 ns
2 41 ns
2 38 ns
2 34 ns
NOTES:
1. All voltages referenced to device GND.
2. AC measurements assume RL = 500Ω, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = 3V.
3. For functional tests VO ≥ 4.0V is recognized as a logic “1”, and VO ≤ 0.5V is recognized as a logic “0”.
TABLE 5. BURN-IN AND OPERATING LIFE TEST, DELTA PARAMETERS (+25oC)
PARAMETER
GROUP B
SUBGROUP
DELTA LIMIT
ICC 5 6µA
IOL/IOH
5 -15% of 0 Hour
Spec Number 518603
494

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