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PDF OP4012B Data sheet ( Hoja de datos )
| Número de pieza | OP4012B | |
| Descripción | Optical Timing Clock | |
| Fabricantes | RF Monolithics | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de OP4012B (archivo pdf) en la parte inferior de esta página. Total 7 Páginas | ||
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Preliminary
®
• Quartz SAW Stabilized Differential Output Technology
• Very Low Jitter Fundamental-Mode Operation at 644.53125 MHz
• Voltage Tunable for Phase Locked Loop Applications
• Timing Reference for 10G Optical Ethernet Communications Systems
The OP4012B is a voltage-controlled SAW clock (VCSC) designed for phase-locked loop (PLL) applications
in optical data communications systems. The differential outputs of the OP4012B are generated by high-Q,
fundamental mode quartz surface acoustic wave (SAW) technology. This technique provides very low output
jitter and phase noise, plus excellent immunity to power supply noise. The OP4012B differential outputs fea-
ture ±1% symmetry, and can be DC-configured to drive a wide range of high-speed logic families. The
OP4012B is packaged in a hermetic metal-ceramic LCC.
Absolute Maximum Ratings
Rating
DC Suppy Voltage
Tune Voltage
Case Temperature
Value
0 to 5.5
0 to 5.5
-55 to 100
Units
Vdc
Vdc
°C
OP4012B
644.53125 MHz
Optical
Timing Clock
SMC-08
Electrical Characteristics
Operating Frequency
Characteristic
Absolute Frequency
Tuning Range
Tuning Voltage
Tuning Linearity
Tuning Sensitivity
Modulation Bandwidth
Sym
fO
df/dv
Notes
1
2
1
1, 8
2
Minimum
±100
0
100
125
Typical
644.53125
±5
265
Maximum
3.3
260
Units
MHz
ppm
Vdc
%
ppm/V
kHz
Q and Q Output
Voltage into 50 Ω (VSWR ≤ 1.2)
Operating Load VSWR
Symmetry
Harmonic Spurious
Nonharmonic Spurious
Phase Noise
@ 100 Hz offset
@ 1 kHz offset
@ 10 kHz offset
Noise Floor
Q and Q Jitter
RMS Jitter
No Noise on VCC
200 mVP-P Noise, from 1 MHz to ½ fO on VCC
Input Impedence (Tuning Port)
Output DC Resistance (between Q & Q)
DC Power Supply
Operating Voltage
Operating Current
Operating Case Temperature
Lid Symbolization (YY=Year, WW=Week)
VO
VCC
ICC
TC
1,3
1,3
3, 4, 5
3, 4, 6
3, 4, 6, 7
3, 6
3, 6
3, 6
3, 6
3, 4, 6, 7
3, 4, 6, 7
3
1, 3
1, 3
1, 3
1, 3
0.60
49
1
50
3.13
-70
-100
-125
-150
2
12
12
3.3 or 5.0
-40°C
RFM OP4012B YYWW
1.1
2:1
51
-30
-60
5.25
70
+85°C
VP-P
%
dBc
dBc
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
ps
psP-P
psP-P
KΩ
KΩ
Vdc
mA
°C
CAUTION: Electrostatic Sensitive Device. Observe precautions for handling. COCOM CAUTION: Approval by the U.S. Department of Commerce is required
prior to export of this device.
Notes:
1. Unless otherwise noted, all specifications include the combined effects of load VSWR, VCC and TC.
2. Net tuning range after tuning out the effects of initial manufacturing tolerances, VSWR pushing/pulling, VCC, TC and aging.
3. The internal design, manufacturing processes, and specifications of this device are subject to change without notice.
4. Specified only for a balanced load with a VSWR < 1.2 ( 50 ohms each side), and a VCC = 3.0 Vdc.
5. Symmetry is defined as the width in (% of total period) measure at 50% of the peak-to-peak voltage of either output.
6. Jitter and other noise outputs due to power supply noise or mechanical vibration are not included in this specification except where noted.
7. Applies to period jitter of either differential output. Measured with a Tektronix CSA803 signal analyzer with at least 1000 samples.
8. See Figure 4.
9. One or more of the following United States patents apply: 4, 616,197; 4,670,681; 4,760,352.
RF Monolithics, Inc. Phone: (972) 233-2903
Fax: (972) 387-8148
RFM Europe
Phone: 44 1963 251383
Fax: 44 1963 251510
©2001 by RF Monolithics, Inc. The stylized RFM logo are registered trademarks of RF Monolithics, Inc.
E-mail: [email protected]
http://www.rfm.com
OP4012B-041003
Page 1 of 7
1 page  
644.53125 MHz
Optical Timing Clock
Table 1 provides R1 and R2 values for six high-speed logic families commonly used in optical data communications systems.
Note that the OP4012B can be used with logic families that run from a negative power supply voltage by simply using a
negative VLOAD voltage.
Load Type
10k 3.3 V PECL
100k 3.3 V PECL
10k 5 V PECL
100k 5 V PECL
10k -5 V NECL
100k -5 V NECL
VDC
1.95
1.88
3.65
3.58
-1.30
-1.42
R1 R2
120 91
120 91
180 68
180 68
240 62
240 62
VLOAD
3.3 V
3.3 V
5.0 V
5.0 V
-5.0 V
-5.0 V
Table 1
OP4012B Enable/Disable
Pin 3 on the OP4012B is the enable/disable control pin for the clock outputs. When Pin 3 is grounded, full output power is
available from the clock. When Pin 3 is pulled to Vcc, the power on the clock outputs is decreased at least 25 dB.
PLL for Generating a High Stability 644.53125 MHz Clock
External
Reference
Internal
Reference
(holdover)
Phase
Detector
Loop Filter
Tune
÷N
+Vcc
OP4012B
Q
Q
Figure 6
Example OP4012B Phase-Locked Loop Application
One of the most important applications for the OP4012B is in a PLL circuit used to generate a very high quality
644.53125 MHz clock. The PLL combines the long-term stability of a precision external or internal 20.1416 MHz reference
clock with the very low jitter and phase noise of the OP4012B. A block diagram of the PLL is shown in Figure 6. A sample
of the OP4012B output is divided by 32 and is compared to 20.1416 MHz reference clock in the phase detector. The loop
filter at the output of the phase detector is set to a very low bandwidth (less than 50 Hz typical). This imparts the long-term
stability of the precision 20.1416 MHz reference to the OP4012B without degrading the OP4012B's low jitter and
phase noise.
RF Monolithics, Inc. Phone: (972) 233-2903
Fax: (972) 387-8148
RFM Europe
Phone: 44 1963 251383
Fax: 44 1963 251510
©2001 by RF Monolithics, Inc. The stylized RFM logo are registered trademarks of RF Monolithics, Inc.
E-mail: [email protected]
http://www.rfm.com
OP4012B-041003
Page 5 of 7
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