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NT5CC128M16FP-DIB PDF даташит

Спецификация NT5CC128M16FP-DIB изготовлена ​​​​«Nanya» и имеет функцию, называемую «Industrial and Automotive DDR3(L) 2Gb SDRAM».

Детали детали

Номер произв NT5CC128M16FP-DIB
Описание Industrial and Automotive DDR3(L) 2Gb SDRAM
Производители Nanya
логотип Nanya логотип 

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NT5CC128M16FP-DIB Даташит, Описание, Даташиты
DDR3(L) 2Gb SDRAM
NT5CB(C)256M8FN / NT5CB(C)128M16FP
Nanya Technology Corp.
NT5CB(C)256M8FN / NT5CB(C)128M16FP
Commercial, Industrial and Automotive DDR3(L) 2Gb SDRAM
Features
JEDEC DDR3 Compliant
- 8n Prefetch Architecture
- Differential Clock(CK/) and Data Strobe(DQS/)
- Double-data rate on DQs, DQS and DM
Data Integrity
- Auto Self Refresh (ASR) by DRAM built-in TS
- Auto Refresh and Self Refresh Modes
Power Saving Mode
- Partial Array Self Refresh (PASR)1
- Power Down Mode
Signal Integrity
- Configurable DS for system compatibility
- Configurable On-Die Termination
- ZQ Calibration for DS/ODT impedance accuracy via
external ZQ pad (240 ohm ± 1%)
Signal Synchronization
- Write Leveling via MR settings 7
- Read Leveling via MPR
Interface and Power Supply
- SSTL_15 for DDR3:VDD/VDDQ=1.5V(±0.075V)
- SSTL_1354 for DDR3L:VDD/VDDQ=1.35V(-0.067/+0.1V)
Speed Grade (CL-TRCD-TRP) 2,3
- 2133 Mbps / 14-14-14
- 1866 Mbps / 12-12-12,13-13-13
- 1600 Mbps / 11-11-11
Options
Temperature Range (Tc) 5
- Commercial Grade = 0~95
- Industrial Grade (-I) = -40~95
- Automotive Grade 2 (-H) = -40~105
- Automotive Grade 3 (-A) = -40~95
Programmable Functions
CAS Latency (5/6/7/8/9/10/11/12/13/14)
CAS Write Latency (5/6/7/8/9/10)
Additive Latency (0/CL-1/CL-2)
Write Recovery Time (5/6/7/8/10/12/14/16)
Burst Type (Sequential/Interleaved)
Burst Length (BL8/BC4/BC4 or 8 on the fly)
Self RefreshTemperature Range(Normal/Extended)
Output Driver Impedance (34/40)
On-Die Termination of Rtt_Nom(20/30/40/60/120)
On-Die Termination of Rtt_WR(60/120)
Precharge Power Down (slow/fast)
Packages / Density Information
Lead-free RoHS compliance and Halogen-free
Density and Addressing
2Gb
(Org. / Package)
Length x Width Ball pitch
(mm)
(mm)
256Mbx8
78-ball
TFBGA
8.00 x 10.50
0.80
128Mbx16
96-ball
TFBGA
9.00 x 13.00
0.80
Organization
Bank Address
Auto precharge
BL switch on the fly
Row Address
Column Address
Page Size
tREFI(us) 5
tRFC(ns) 6
256Mb x 8
128Mb x 16
BA0 BA2
BA0 BA2
A10 / AP
A12 / 
A10 / AP
A12 / 
A0 A14
A0 A9
A0 A13
A0 A9
1KB 2KB
Tc<=85:7.8, Tc>85:3.9
160ns
NOTE 1
NOTE 2
NOTE 3
NOTE 4
NOTE 5
NOTE 6
NOTE 7
Default state of PASR is disabed. This is enabled by using an electrical fuse. Please contact with NTC for the demand.
The timing specification of high speed bin is backward compatible with low speed bin.
Please refer to ordering information for the deailts (DDR3, DDR3L, DDR3L RS).
SSTL_135 compatible to SSTL_15. That means 1.35V DDR3L are backward compatible to 1.5V DDR3 parts. 1.35V DDR3L-RS parts are exceptional
and unallowable to be compatible to 1.35V DDR3L and 1.5V DDR3 parts.
If TC exceeds 85°C, the DRAM must be refreshed externally at 2x refresh, which is a 3.9us interval refresh rate. Extended SRT or ASR must be enabled.
Violating tRFC specification will induce malfunction.
Only Support prime DQs feedback for each byte lane.
Version 1.6
04/2014
1 Nanya Technology Cooperation ©
NTC has the rights to change any specifications or product without notification.
All Rights Reserved.









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NT5CC128M16FP-DIB Даташит, Описание, Даташиты
DDR3(L) 2Gb SDRAM
NT5CB(C)256M8FN / NT5CB(C)128M16FP
Fundamental AC Specifications Core Timing
DDR3-2133, DDR3(L)-1866, DDR3(L)-1600 and DDR3(L)-1333
DDR3-2133
Speed Bins
14-14-14
DDR3(L)-1866
12-12-12
13-13-13
DDR3(L)-1600
11-11-11
DDR3(L)-1333
9-9-9
10-10-10
Unit
Parameter Min Max Min Max Min Max Min Max Min Max Min Max
tAA 13.09 20 12.84 20.0 13.91 20 13.75 20 13.5 20 15 20 ns
tRCD 13.09 - 12.84 - 13.91 - 13.75 - 13.5 - 15 - ns
tRP 13.09 - 12.84 - 13.91 - 13.75 - 13.5 - 15 - ns
tRC 46.09 - 46.84 - 47.91 - 48.75 - 49.5 - 51 - ns
tRAS
33 9*tREFI 34.0 9*tREFI 34 9*tREFI 35 9*tREFI 36 9*tREFI 36 9*tREFI ns
Speed Bins
Parameter
DDR3(L)-1066 and DDR3(L)-800
DDR3(L)-1066
DDR3(L)-800
7-7-7
8-8-8
5-5-5
6-6-6
Unit
Min Max Min Max Min Max Min Max
tAA 13.125 20 15 20 12.5 20 15 20 ns
tRCD 13.125
-
15
- 12.5 -
15
- ns
tRP 13.125 - 15 - 12.5 - 15 - ns
tRC 50.625 - 52.5 - 50 - 52.5 - ns
tRAS
37.5 9*tREFI 37.5 9*tREFI 37.5 9*tREFI 37.5 9*tREFI ns
Version 1.6
04/2014
2 Nanya Technology Cooperation ©
All Rights Reserved.









No Preview Available !

NT5CC128M16FP-DIB Даташит, Описание, Даташиты
DDR3(L) 2Gb SDRAM
NT5CB(C)256M8FN / NT5CB(C)128M16FP
Descriptions
The 2Gb Double-Data-Rate-3 (DDR3(L)) is double data rate architecture to achieve high-speed operation. It is
internally configured as an eight bank DRAMs.
The 2Gb chip is organized as 32Mbit x 8 I/Os x 8 banks or 16Mbit x 16 I/Os x 8 bank devices. These
synchronous devices achieve high speed double-data-rate transfer rates of up to 1866 Mb/sec/pin for general
applications.
The chip is designed to comply with all key DDR3(L) DRAM key features and all of the control and address
inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross
point of differential clocks (CK rising and  falling). All I/Os are synchronized with a single ended DQS or
differential DQS pair in a source synchronous fashion.
These devices operate with a single 1.5V ± 0.075V or 1.35V -0.067V/+0.1V power supply and are available in
BGA packages.
Version 1.6
04/2014
3 Nanya Technology Cooperation ©
All Rights Reserved.










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Номер в каталогеОписаниеПроизводители
NT5CC128M16FP-DIIndustrial and Automotive DDR3(L) 2Gb SDRAMNanya
Nanya
NT5CC128M16FP-DIAIndustrial and Automotive DDR3(L) 2Gb SDRAMNanya
Nanya
NT5CC128M16FP-DIBIndustrial and Automotive DDR3(L) 2Gb SDRAMNanya
Nanya
NT5CC128M16FP-DIHIndustrial and Automotive DDR3(L) 2Gb SDRAMNanya
Nanya

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