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GN25L95 PDF даташит

Спецификация GN25L95 изготовлена ​​​​«Semtech» и имеет функцию, называемую «2.5 Gbps CMOS Burst Mode Laser Driver & Limiting Post Amplifier».

Детали детали

Номер произв GN25L95
Описание 2.5 Gbps CMOS Burst Mode Laser Driver & Limiting Post Amplifier
Производители Semtech
логотип Semtech логотип 

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GN25L95 Даташит, Описание, Даташиты
GN25L95
2.5 Gbps CMOS Burst Mode Laser Driver & Limiting Post
Amplifier with On-Chip Digital Diagnostic Monitoring
Main Features
100 mA bias current and 90 mA
modulation current output drive capability
On-chip Digital Diagnostic Monitoring
(DDMI)
Automatic Mean Power and Automatic
Extinction Ratio control
Fast burst-mode loop settling time
Current DAC output for APD bias control
TX_SD and rogue ONU alarm function
True average Tx burst power monitor
Tx fault detection and safety logic
Power down and sleep mode support
CSFP I2C addressing support
Applications
EPON & GPON FTTh ONU/ONT
BOSA-on-Board ONU
SFF/SFP & CSFP modules
General Description
The GN25L95 is a combined burst mode
laser driver and limiting post amplifier
designed for fiber optic transceiver modules.
The GN25L95 features on-chip digital
diagnostic monitoring and digital set-up. This
enables a complete solution for SFP/SFF
optical transceiver modules.
A fully compliant SFF-8472 digital
diagnostic monitoring solution can be
realised by connecting an external 8k
EEPROM.
The GN25L95 features automatic mean
power and automatic extinction ratio control
functions for robust and reliable control of
laser operating conditions over temperature.
Auto-ranging A/D converters with digitized
monitoring, an internal temperature sensor
and an on-chip DAC for controlling an
external APD bias circuit are also included.
Consuming 90 mA from a 3.3 V supply the
GN25L95 is packaged in a 4x4 mm QFN 28
pin RoHS package rated from -40 to +95 °C.
Block Diagram
Package
VCC_TX VCC_RX VCC_DIG LOS/SD
RXOUT+
RXOUT-
BEN+
BEN-
CML
BURST
ENABLE
Limiter
LOS
&
Filter
RXIN+
Gain
RXIN-
APD
DAC
APD_DAC
TXIN+
TXIN-
RX_SLEEP
SDA
SCL
EE_SDA
EE_SCL
DATA
INPUT
STATE MACHINE
DDMI
CONTROLLER
NVM
DIGITAL
INTERFACE
EEPROM
CONTROLLER
MOD
DRIVER
APC & AUTO ER CONTROL
BIAS
DRIVER
Burst
Mean
Power
Monitor
SAFETY LOGIC &
CONTROL
TX
SD
DIGITAL
ADC &
TEMP
SENSOR
LASER+
LASER-
BIAS+
BIAS-
TX_SD
MPD
RSSI_IN
ADC_IN
GND TX_DISABLE/ TX_FAULT
TX_SLEEP
28 27 26 25 24 23 22
SD/LOS 1
21 TX_SD
RXOUT- 2
20 TX_FAULT
RXOUT+ 3
VCC_DIG 4
GN25L95
19 LASER+
18 LASER-
SDA 5
17 VCC_TX
SCL 6
16 BIAS+
EE_SDA 7
15 BIAS-
8 9 10 11 12 13 14
Figure 1 – GN25L95 Functional Block diagram
GN25L95
Advanced Datasheet
Rev 1.0 – 28 January 2013
www.semtech.com
Figure 2 – GN25L95 Package
1
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GN25L95 Даташит, Описание, Даташиты
Table of Contents
Main Features ......................................................................................................................................... 1
Applications ............................................................................................................................................. 1
General Description ................................................................................................................................ 1
Block Diagram ......................................................................................................................................... 1
Package .................................................................................................................................................. 1
Table of Contents .................................................................................................................................... 2
Table of Figures ...................................................................................................................................... 4
Package Diagram & Pin Descriptions ..................................................................................................... 6
Typical Operating Characteristics ......................................................................................................... 15
Functional Block Diagram ..................................................................................................................... 16
Functional Description........................................................................................................................... 17
Power Supplies and Start-up Sequence ........................................................................................... 17
GN25L95 State Machine Controller .................................................................................................. 18
Modes of Operation ........................................................................................................................... 19
Internal NVM mode ........................................................................................................................ 19
External EEPROM mode ............................................................................................................... 20
External MCU mode....................................................................................................................... 21
Start-up Sequence ......................................................................................................................... 22
Transmitter Features ......................................................................................................................... 24
Transmitter Input Stage ................................................................................................................. 24
Modulation Stage ........................................................................................................................... 27
MOD_DAC ..................................................................................................................................... 28
Modulation LUT.............................................................................................................................. 29
Automatic Extinction Ratio Control ................................................................................................ 30
MOD_MAX ..................................................................................................................................... 31
Active Back Termination ................................................................................................................ 32
Bias Stage...................................................................................................................................... 33
APCSET_DAC ............................................................................................................................... 33
APCSET LUT................................................................................................................................. 34
BIAS_DAC ..................................................................................................................................... 35
Bias LUT ........................................................................................................................................ 36
Burst Control Stage........................................................................................................................ 37
APC_CLOCK_SET ........................................................................................................................ 38
DIG_AVG_SET .............................................................................................................................. 38
APC Fast Start-up Algorithm ......................................................................................................... 40
COUNT_INC .................................................................................................................................. 41
BIAS_MAX ..................................................................................................................................... 41
MD_MAX........................................................................................................................................ 43
Transmitted Signal Detect Status Output ...................................................................................... 44
Rogue ONU Monitoring.................................................................................................................. 45
GPON Power Levelling .................................................................................................................. 48
Tx Crossing Point Adjust................................................................................................................ 48
Eye Safety Stage ........................................................................................................................... 50
The APC loop and Auto ER loop are protected by a single-point of failure check such that any
opens or shorts to these control loops causes a TX_FAULT condition as required by IEC-60825.
The GN25L95 circuit response to single point failures is shown in ............................................... 50
Alarms and Warnings..................................................................................................................... 50
TX_FAULT Output ......................................................................................................................... 50
Circuit Responses to Single Points Of Failure............................................................................... 53
Safety Logic Timing ....................................................................................................................... 55
TX_DISABLE on Rx LOS .............................................................................................................. 59
Receiver Features ............................................................................................................................. 60
Receiver Input Stage ..................................................................................................................... 60
Receiver CML Output Stage.......................................................................................................... 60
Receiver Digital Control Functions Block Diagram........................................................................ 61
Receiver Data Output Polarity Invert Function .............................................................................. 61
Receiver Data Output Amplitude Control....................................................................................... 61
Receiver Data Output Slew Control............................................................................................... 62
GN25L95
Advanced Datasheet
Rev 1.0 – 28 January 2013
2
Proprietary & Confidential









No Preview Available !

GN25L95 Даташит, Описание, Даташиты
Receiver Filter Stage ..................................................................................................................... 62
Optimising the Receiver Signal Path Settings ............................................................................... 62
Signal Detect/Loss of Signal Stage ............................................................................................... 63
Setting the LOS Assert Level......................................................................................................... 63
Setting the LOS Hysteresis............................................................................................................ 63
LOS/SD Output Type ..................................................................................................................... 65
LOS/SD Output Polarity ................................................................................................................. 65
Receiver Output Squelch Function ................................................................................................ 65
APD DAC Control .......................................................................................................................... 66
Sleep Modes...................................................................................................................................... 67
Software control of Sleep Modes ................................................................................................... 67
Hardware control of Sleep Modes ................................................................................................. 67
Digital Control & Monitoring Features ............................................................................................... 69
Digital I2C Interface ........................................................................................................................ 69
Address Decoding.......................................................................................................................... 69
Write Transaction........................................................................................................................... 70
Writing values to 16-bit DACs........................................................................................................ 70
Read Transaction........................................................................................................................... 71
I2C Address Change ...................................................................................................................... 72
Slave I2C Timeout / Recovery........................................................................................................ 73
Memory Map .................................................................................................................................. 74
Password Protection Levels .......................................................................................................... 74
Copying register memory to NVM.................................................................................................. 75
State Machine Reset Function....................................................................................................... 76
Internal Diagnostic Monitoring ........................................................................................................... 77
Mapping of the ADCs into Register Memory ................................................................................. 77
Temperature Monitor ..................................................................................................................... 78
External ADC input ........................................................................................................................ 78
Tx Bias Current Monitor ................................................................................................................. 79
Tx Power Monitor........................................................................................................................... 80
Rx Power Monitor .......................................................................................................................... 81
Tx Modulation Current Monitor ...................................................................................................... 82
Tx Supply Voltage Monitor............................................................................................................. 83
Rx Supply Voltage Monitor ............................................................................................................ 83
Register Map ......................................................................................................................................... 84
A0h Memory Area .......................................................................................................................... 84
A2h Memory Area .......................................................................................................................... 85
A2h Lower (00h to 7Fh) Memory Area Register Map .................................................................... 86
A2h Upper (80h to FFh) Memory Area Register Map.................................................................... 94
A2h Table 2 – GN25L95 Control Settings ..................................................................................... 96
A2h Table 4 – GN25L95 Modulation Look-Up Table................................................................... 109
A2h Table 5 – GN25L95 Bias Look-Up Table ............................................................................. 110
A2h Table 6 – GN25L95 APCSET DAC and APD DAC Look-Up Tables ................................... 111
Applications Information...................................................................................................................... 112
Applications ..................................................................................................................................... 112
EPON FTTh ONU Transceiver Module ....................................................................................... 112
GPON FTTh ONU Transceiver Module ....................................................................................... 113
GPON APD BOSA-on-Board Application .................................................................................... 114
SFP DDMI Transceiver Module ................................................................................................... 115
Package Information ........................................................................................................................... 116
Ordering Information ........................................................................................................................... 117
Contact Information............................................................................................................................. 118
GN25L95
Advanced Datasheet
Rev 1.0 – 28 January 2013
3
Proprietary & Confidential










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