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PDF HCTS21DMSR Data sheet ( Hoja de datos )
| Número de pieza | HCTS21DMSR | |
| Descripción | Radiation Hardened Dual 4-Input AND Gate | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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HCTS21MS
October 1995
Radiation Hardened
Dual 4-Input AND Gate
Features
Pinouts
• 3 Micron Radiation Hardened SOS CMOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm2/mg
• Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day
(Typ)
• Dose Rate Survivability: >1 x 1012 RAD (Si)/s
• Dose Rate Upset >1010 RAD(Si)/s 20ns Pulse
• Latch-Up Free Under Any Conditions
• Military Temperature Range: -55oC to +125oC
• Significant Power Reduction Compared to LSTTL ICs
14 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-183S CDIP2-T14, LEAD FINISH C
TOP VIEW
A1 1
B1 2
NC 3
C1 4
D1 5
Y1 6
GND 7
14 VCC
13 D2
12 C2
11 NC
10 B2
9 A2
8 Y2
• DC Operating Voltage Range: 4.5V to 5.5V
• LSTTL Input Compatibility
- VIL = 0.8V Max
- VIH = VCC/2 Min
• Input Current Levels Ii ≤ 5µA at VOL, VOH
Description
The Intersil HCTS21MS is a Radiation Hardened Dual Input AND
Gate. A high on all inputs forces the output to a High state.
14 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
(FLATPACK) MIL-STD-183S CDFP3-F14, LEAD FINISH C
TOP VIEW
A1
B1
NC
C1
D1
Y1
GND
1 14
2 13
3 12
4 11
5 10
69
78
VCC
D2
C2
NC
B2
A2
Y2
The HCTS21MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of radia-
tion hardened, high-speed, CMOS/SOS Logic Family.
The HCTS21MS is supplied in a 14 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
Functional Diagram
An
Bn
Ordering Information
PART
NUMBER
TEMPERATURE SCREENING
RANGE
LEVEL
PACKAGE
HCTS21DMSR -55oC to +125oC Intersil Class 14 Lead SBDIP
S Equivalent
Cn
Dn
TRUTH TABLE
Yn
HCTS21KMSR -55oC to +125oC Intersil Class
S Equivalent
HCTS21D/
Sample
+25oC
Sample
HCTS21K/
Sample
+25oC
Sample
HCTS21HMSR
+25oC
Die
14 Lead Ceramic
Flatpack
14 Lead SBDIP
14 Lead Ceramic
Flatpack
Die
INPUTS
OUTPUTS
An Bn Cn Dn
Yn
LXXX
L
XLXX
L
XXLX
L
XXXL
L
HHHH
H
NOTE: L = Logic Level Low, H = Logic level High, X = Don’t Care
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com | Copyright © Intersil Corporation 1999
1
Spec Number 518618
File Number 3053.1
1 page  
Specifications HCTS21MS
TABLE 8. STATIC AND DYNAMIC BURN-IN TEST CONDITIONS
OSCILLATOR
OPEN
GROUND
1/2 VCC = 3V ± 0.5V VCC = 6V ± 0.5V
50kHz
25kHz
STATIC BURN-IN I TEST CONDITIONS
3, 6, 8, 11
1, 2, 4, 5, 7, 9, 10, 12,
13
-
14 - -
STATIC BURN-IN II TEST CONNECTIONS
3, 6, 8, 11
7
-
1, 2, 4, 5, 9, 10, 12,
-
13, 14
-
DYNAMIC BURN-IN TEST CONNECTIONS
-
7
3, 6, 8, 11
14 1, 2, 4, 5, 9, 10,
-
12, 13
NOTE:
1. Each pin except VCC and GND will have a resistor of 10KΩ ± 5% for static burn-in.
2. Each pin except VCC and GND will have a resistor of 1KΩ ± 5% for dynamic burn-in.
TABLE 9. IRRADIATION TEST CONNECTIONS
OPEN
GROUND
VCC = 5V ± 0.5V
3, 6, 8, 11 7 1, 2, 4, 5, 9, 10, 12, 13, 14
NOTE: Each pin except VCC and GND will have a resistor of 47KΩ ± 5% for irradiation testing.
Group E, Subgroup 2, sample size is 4 dice/wafer 0 failures.
Spec Number 518618
5
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet HCTS21DMSR.PDF ] | |
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