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NCP6132A Datasheet Download - ON Semiconductor

Номер произв NCP6132A
Описание Dual Output 3 Phase & 2 Phase Controller
Производители ON Semiconductor
логотип ON Semiconductor логотип 



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NCP6132A Даташит, Описание, Даташиты
NCP6132A, NCP6132B
Product Preview
Dual Output 3 Phase & 2
Phase Controller with
Single SVID Interface for
Desktop and Notebook CPU
http://onsemi.com
Applications
The NCP6132A/NCP6132B dual output three plus two phase buck
solution is optimized for Intel IMVP7 and VR12 compatible CPUs.
The controller combines true differential voltage sensing, differential
inductor DCR current sensing, input voltage feedforward, and
adaptive voltage positioning to provide accurately regulated power for
both Desktop and Notebook applications. The control system is based
on DualEdge pulsewidth modulation (PWM) combined with DCR
current sensing providing the fastest initial response to dynamic load
events and reduced system cost. It also sheds to single phase during
light load operation and can auto frequency scale in light load while
maintaining excellent transient performance.
There are three internal MOSFET drivers inside the chip. One of
these three integrated driver can be configured either to drive core
phase or aux phase. NCP6132A and NCP6132B have almost same
structure except that NCP6132A has two integrated drivers for the
core rail and one integrated driver for auxiliary rail, while the
NCP6132B has all three integrated drivers for the core rail.
MARKING
DIAGRAM
1
1 60
QFN60
CASE 485BB
NCP6132x
AWLYYWWG
x = A or B
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = PbFree Package
ORDERING INFORMATION
Device
NCP6132AMNR2G
NCP6132BMNR2G
Package
QFN60
(PbFree)
Shipping
2500/Tape
& Reel
Features
Meets Intel’s VR12/IMVP7 Specifications
Three Phase CPU Voltage Regulator, and Two Phase Auxiliary
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Voltage Regulator, with Three Internal MOSFET Drivers in Total
Current Mode Dual Edge Modulation for Fastest Initial Response to
Transient Loading
Dual High Performance Operational Error Amplifier
One Digital Soft Start Ramp for Both Rails
Dynamic Reference Injection
Adaptive Voltage Positioning (AVP)
Accurate Total Summing Current Amplifier
Vin Feed Forward Ramp Slope
DAC with Droop Feedforward Injection
Pin Programming for Internal SVID Parameters
Dual High Impedance Differential Voltage and Total
Over Voltage Protection (OVP) & Under Voltage
Current Sense Amplifiers
Protection (UVP)
PhasetoPhase Dynamic Current Balancing
Over Current Protection (OCP)
“Lossless” DCR Current Sensing for Current Balancing
Dual Power Good Output with Internal Delays
Summed Thermally Compensated Inductor Current
Pbfree and Halidefree Packages are Available
Sensing for Droop
True Differential Current Balancing Sense Amplifiers
for Each Phase
Applications
Desktop & Notebook Processors
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
© Semiconductor Components Industries, LLC, 2012
March, 2012 Rev. P1
1
Publication Order Number:
NCP6132A/D







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NCP6132A Даташит, Описание, Даташиты
NCP6132A, NCP6132B
EN
GND
VCC
VDDBP
TSNS
TSNSA
VRHOT#
SDIO
SCLK
ALERT#
VBOOT
VSP
VSN
DROOP
DIFF
FB
COMP
TRBST#
CSSUM
CSREF
CSCOMP
ILIM
IOUT
CSP1
CSP2
CSP3
UVLO & EN
THERMAL
MONITOR
ENABLE
ENABLE
VSPA
VSNA
DACA
DROOPA
AUX VR READY
COMPARATOR
ENABLE
SVID
INTERFACCE
DATA
REGISTERS
ADC
DAC
GND
CSREF
DIFFAMP
1.3 V
ERROR
AMP
+
1.3 V
DAC
AUX
DAC
VSPA
VSNA
VSP
VSN
TRBST
DETECT
DAC
AUX
DAC
AUX OVP
OVP
VRDYA
ENABLE
VSP
VSN
DAC
DROOP
VR READY
COMPARATOR
MUX
VSPA VSNA
VSP VSN
TSNS
TSNSA
IMON
IMONA
IMAX
IMAXA
AUX
DIFFAMP
AUX
DAC
GND
CSREFA
1.3 V
VRDY
VSPA
VSNA
DROOPA
DIFFA
OVPA
OVP
IOUTA
ILIMA
AUX
CS
AMP
+
CSSUMA
CSREFA
CSCOMPA
ILIMA
IOUTA
FBA
AUX
ERROR
AMP
+
1.3 V
CS
AMP
+
CSREF
IOUT
ILIM
MAIN
CURRENT
BALANCE
ENABLE
COMP
OVP
ENABLE
TRBSTA
DETECT
CORE PHASE
GENERATOR
RAMP 1
RAMP 2
RAMP 3
RAMP
GENERATORS
AUX
CURRENT
BALANCE
ENABLE
COMPA
OVPA
RAMPA2
RAMPA1
AUX
PWM
GENERATOR
COMPA
TRBSTA#
CSP1A
CSP2A
CSREFA
BSTA
HGA
SWA
PVCC
LGA
PGND
PWMA
PGND
PVCC
Figure 1. Block Diagram
http://onsemi.com
2







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NCP6132A Даташит, Описание, Даташиты
NCP6132A, NCP6132B
VCC
VDDBP
VRDYA
EN
SDIO
ALERT#
SCLK
VBOOT
ROSC
VRMP
VRHOT#
VRDY
VSN
VSP
DIFF
1 60
15
16
NCP6132A/NCP6132B
Tab: GND
46
45
31
30
PWMA
BSTA
HGA
SWA
LGA
BST2
HG2
SW2
LG2
PVCC
PGND
LG1
SW1
HG1
BST1
Figure 2. QFN60 Pin Diagram
Table 1. QFN60 PIN LIST DESCRIPTION
Pin
No. Symbol
Description
1
VCC
Power for the internal control circuits. A decoupling capacitor is connected from this pin to ground.
2
VDDBP
Digital Logic power. Connect this pin to VCC with 10 W. Connect 0.1 mF capacitor from this pin to
ground
3
VRDYA
Open drain output. High indicates that the aux output is regulating.
4 EN Logic input. Logic high enables both outputs and logic low disables both outputs.
5
SDIO
Serial VID data interface.
6
ALERT#
Serial VID ALERT#.
7
SCLK
Serial VID clock.
8
VBOOT
A resistor to GND on this pin sets the Core and Aux Bootup Voltage
9
ROSC
A resistance from this pin to ground programs the oscillator frequency. This pin supplies a trimmed
output voltage of 2 V.
10
VRMP
Feedforward input of Vin for the ramp slope compensation. The current fed into this pin is used to
control of the ramp of PWM slope
11
VRHOT#
Thermal logic output for over temperature.
12
VRDY
Open drain output. High indicates that the core output is regulating.
13
VSN
Inverting input to the core differential remote sense amplifier.
14
VSP
Noninverting input to the core differential remote sense amplifier.
15
DIFF
Output of the core differential remote sense amplifier.
16
TRBST#
Compensation pin for the load transient boost.
17 FB Error amplifier voltage feedback for core output
18
COMP
Output of the error amplifier and the inverting inputs of the PWM comparators for the core output.
19
IOUT
Total output current monitor for core output. Short it to GND if IMON function is not needed.
20 ILIM Over current shutdown threshold setting for core output. Resistor to CSCOMP to set threshold.
21
DROOP
Used to program droop function for core output. It’s connected to the resistor divider placed between
CSCOMP and CSREF summing node.
22
CSCOMP
Output of total current sense amplifier for core output.
http://onsemi.com
3










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