PDF HCTS86KMSR Data sheet ( Hoja de datos )

Número de pieza	HCTS86KMSR
Descripción	Radiation Hardened Quad 2-Input Exclusive OR Gate
Fabricantes	Intersil Corporation
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No Preview Available ! HCTS86MS October 1995 Radiation Hardened Quad 2-Input Exclusive OR Gate Features Pinouts • 3 Micron Radiation Hardened SOS CMOS • Total Dose 200K RAD (Si) • SEP Effective LET No Upsets: >100 MEV-cm2/mg • Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day (Typ) • Dose Rate Survivability: >1 x 1012 RAD (Si)/s • Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse • Latch-Up Free Under Any Conditions • Military Temperature Range: -55oC to +125oC • Signiﬁcant Power Reduction Compared to LSTTL ICs 14 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP) MIL-STD-1835 CDIP2-T14, LEAD FINISH C TOP VIEW A1 1 B1 2 Y1 3 A2 4 B2 5 Y2 6 GND 7 14 VCC 13 B4 12 A4 11 Y4 10 B3 9 A3 8 Y3 • DC Operating Voltage Range: 4.5V to 5.5V • LSTTL Input Compatibility - VIL = 0.8V Max - VIH = VCC/2 Min • Input Current Levels Ii ≤ 5µA at VOL, VOH Description The Intersil HCTS86MS is a Radiation Hardened Quad 2-Input Exclusive OR Gate. A high on any one input exclusively will change the output to a High state. The HCTS86MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of radia- tion hardened, high-speed, CMOS/SOS Logic Family. The HCTS86MS is supplied in a 14 lead Ceramic ﬂatpack (K sufﬁx) or a SBDIP Package (D sufﬁx). Ordering Information 14 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE (FLATPACK) MIL-STD-1835 CDFP3-F14, LEAD FINISH C TOP VIEW A1 B1 Y1 A2 B2 Y2 GND 1 14 2 13 3 12 4 11 5 10 69 78 VCC B4 A4 Y4 B3 A3 Y3 Functional Diagram An (1, 4, 9, 12) Bn (2, 5, 10, 13) Yn (3, 6, 8, 11) PART NUMBER TEMPERATURE SCREENING RANGE LEVEL PACKAGE HCTS86DMSR -55oC to +125oC Intersil Class 14 Lead SBDIP S Equivalent HCTS86KMSR -55oC to +125oC Intersil Class 14 Lead Ceramic S Equivalent Flatpack HCTS86D/ Sample +25oC Sample 14 Lead SBDIP HCTS86K/ Sample +25oC Sample 14 Lead Ceramic Flatpack HCTS86HMSR +25oC Die Die TRUTH TABLE INPUTS OUTPUTS An Bn Yn LLL L HH HLH HH L NOTE: L = Logic Level Low, H = Logic level High CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 \| Copyright © Intersil Corporation 1999 1 Spec Number 518623 File Number 2249.2 1 page Speciﬁcations HCTS86MS TABLE 8. STATIC AND DYNAMIC BURN-IN TEST CONNECTIONS OSCILLATOR OPEN GROUND 1/2 VCC = 3V ± 0.5V VCC = 6V ± 0.5V 50kHz 25kHz STATIC BURN-IN I TEST CONNECTIONS (Note 1) 3, 6, 8, 11 1, 2, 4, 5, 7, 9, 10, 12, 13 - 14 - - STATIC BURN-IN II TEST CONNECTIONS (Note 1) 3, 6, 8, 11 7 - 1, 2, 4, 5, 9, 10, 12, - 13, 14 - DYNAMIC BURN-IN TEST CONNECTIONS (Note 2) - 7 3, 6, 8, 11 14 1, 2, 4, 5, 9, 10, - 12, 13 NOTES: 1. Each pin except VCC and GND will have a resistor of 10kΩ ± 5% for static burn-in. 2. Each pin except VCC and GND will have a resistor of 1KΩ ± 5% for dynamic burn-in TABLE 9. IRRADIATION TEST CONNECTIONS OPEN GROUND VCC = 5V ± 0.5V 3, 6, 8, 11 7 1, 2, 4, 5, 9, 10, 12, 13, 14 NOTE: Each pin except VCC and GND will have a resistor of 47KΩ ± 5% for irradiation testing. Group E, Subgroup 2, sample size is 4 dice/wafer 0 failures. Spec Number 518623 5 5 Page

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