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PDF SAF82520-P Data sheet ( Hoja de datos )
| Número de pieza | SAF82520-P | |
| Descripción | High-Level Serial Communications Controller | |
| Fabricantes | Siemens | |
| Logotipo |  |
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High-Level Serial
Communications Controller (HSCC)
1 Features
Two independent HDLC channels
Implementation of X.25 LAPB/LAPD protocol
Programmable timeout and retry conditions
FIFO buffers for efficient transfer of data packets
Digital phase-locked loop for each channel
Baudrate generator and oscillator
Different modes for clock recovery and data encoding
High-speed data rate (up to 4 MHz)
Supports bus configuration by collision resolution
Telecom-specific features programmable
8-bit parallel µP interface
Advanced CMOS technology
Low power consumption; active: 25 mW at 4 MHz
standby: 3 mW
SAB 82520: operating temperature 0 to 70 ˚C
SAF 82520: operating temperature – 40 to 85 ˚C
P-LCC-28-R
SAB 82520
SAF 82520
P-DIP-28
SAB 82520, a High-level Serial Communications Controller (HSCC), has been designed to
free the user from tasks occurring in communication via networks and trunk lines.
SAB 82520 is an X.25 LAPB/LAPD controller which, to a large degree performs
communications procedures independently of CPU support.
A parallel processor bus constitutes the µC system. The communications interface is
implemented by two full-duplex HDLC channels, which can be operated independently from
one another. The HSCC is connected to the transmission line via additional line drivers or
modems. External logic is cost-effective because clock recovery can be performed by an on-
chip oscillator, DPLL circuits and a programmable baudrate generator.
Type
SAB 82520-N
SAB 82520-P
SAF 82520-N
SAF 82520-P
Ordering Code
Q67100-H8400
Q67100-H8014
Q67100-H8610
Q67100-H8512
Package
P-LCC-28 (SMD)
P-DIP-28
P-LCC-28 (SMD)
P-DIP-28
Semiconductor Group
5
03.94
1 page  
SAB 82520
SAF 82520
Pin Definitions and Functions (cont’d)
Pin No. Symbol
16 ALE
17 CS
18 T × CLK B
19 T × CLK A
Input (I) Functions
Output (O)
I Address Latch Enable
A high on this line indicates an address on the external
address data bus, selecting one of the HSCC internal
sources or destinations.
I Chip Select
A low on this signal selects the HSCC for a read/write
operation.
I/O Transmit Clock
I/O These pins can be programmed in several different
modes of operation. T × CLK may supply the transmit
clock for the respective channel, a receive strobe
signal (T × CLK A) and a transmit strobe signal (T ×
CLK B) or a frame synchronization signal (T × CLK A,
clock mode 5). Programmed as outputs, T × CLK
supply the transmit clock of the respective channel or
a tristate control signal, indicating the programmed
transmit time slot (T × CLK B, clock mode 5).
20
R × CLK B
I
21
R × CLK A
I
22 VDD
23 WR
24 RD
I
I
Receive Clock
These pins can be programmed in several different
modes of operation. In each channel R × CLK may
supply the receive clock, the receive and transmit
clock, the clock for the baud rate generator or the clock
for the DPLL. They also can be programmed for use as
a crystal oscillator.
Power
+ 5 V power supply.
Write
This signal indicates a write operation.
Read
This signal indicates a read operation.
Semiconductor Group
9
5 Page 
SAB 82520
SAF 82520
Data in the I field of the frames are temporarily stored in the RFIFO. The HDLC control field as
well as additional information can be read from special registers.
According to the selected programming mode, the HSCC can perform a two byte or one byte
address recognition. The higher ranking address byte of a two byte address will be compared
with the fixed value FEH and/or FCH as well as two Bit 1 will thereby be excluded from the
address comparison and is instead interpreted as a command/response bit, depending on the
programming of the RAH1 register (CRI bit). Similarly, two comparison values can be entered
into special registers (RAL1, RAL2) for the lower ranking address byte. A valid address will be
recognized in the case where the higher ranking and lower ranking address bytes correspond
to one of the comparison values. Thus, the HSCC can be called with a maximum of six address
combinations, however, only the LAP identified through the address combination RAH1, RAL1
will be processed in the auto mode.
In case of a one byte address, RAL1 and RAL2 will be used as comparison registers.
According to LAP B, the value in RAL1 will be interpreted as command and the value in RAL2
as response.
Note: In case of a one-byte address the value of RAH1 must be set to 00H.
Non-Auto Mode
Characteristics: Address recognition, random window size.
All frames with a valid address comparison are forwarded directly to the µC. Up to 64 data
bytes or two complete frames can be temporarily stored in the HSCC. Data in the I field is
temporarily stored in the RFIFO. The HDLC control field and additional information can be read
from special registers.
Transparent Mode
Characteristics: Address recognition high byte.
Only the higher address byte in a two byte address will be compared. Data in the I field is stored
temporarily in the RFIFO. The second address byte can be read from the receive address byte
low register 1 (RAL1), while the HDLC control field can be read from the receive HDLC control
register (RHCR) and additional information from the receive status register (RSTA). Since the
address compare procedure is omitted for one byte address, each frame will be stored.
Extended Transparent Mode 0
Characteristics: No address recognition.
The entire frame between the start flag and the first CRC byte is stored in the RFIFIO. In
addition, the first byte after the start flag can be read from the RAL1, the second byte from the
RHCR, and additional information from the RSTA.
Semiconductor Group
15
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SAF82520-P.PDF ] | |
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