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PDF H27U518S2C Data sheet ( Hoja de datos )
| Número de pieza | H27U518S2C | |
| Descripción | 512 Mbit (64 M x 8 bit) NAND Flash | |
| Fabricantes | Hynix | |
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1
H27U518S2C Series
512 Mbit (64 M x 8 bit) NAND Flash
512 Mb NAND Flash
H27U518S2C
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev 1.0 / Dec. 2008
1
1 page  
1PrePreliminaryeee
H27U518S2C Series
512 Mbit (64 M x 8 bit) NAND Flash
VCC
CE IO0~IO7
WE
RE R/B
ALE
CLE
WP
VSS
Figure 1 : Logic Diagram
IO7 - IO0
Data Input / Outputs
CLE Command latch enable
ALE Address latch enable
CE Chip Enable
RE Read Enable
WE Write Enable
WP Write Protect
R/B Ready / Busy
Vcc Power Supply
Vss Ground
NC No Connection
Table 1 : Signal Names
Rev 1.0 / Dec. 2008
5
5 Page 
1PrePreliminaryeee
H27U518S2C Series
512 Mbit (64 M x 8 bit) NAND Flash
3. DEVICE OPERATION
3.1 Page Read.
Upon initial device power up, the device defaults to Read1(00h/01h) mode. This operation is also initiated by writing 00h
to the command register along with followed by the four address input cycles. Once the command is latched, it does not
need to be written for the following page read operation.
Three types of operations are available: random read, serial page read and sequential row read.
The random read mode is enabled when the page address is changed. The 528 bytes (x8 device) of data within the se-
lected page are transferred to the data registers in less than access random read time tR. The system controller can detect
the completion of this data transfer tR by analyzing the output of R/B pin. Once the data in a page is loaded into the reg-
isters, they may be read out in 30 ns cycle time by sequentially pulsing RE. High to low transitions of the RE clock output
the data stating from the selected column address up to the last column address.
After the data of last column address is clocked out, the next page is automatically selected for sequential row read.
Waiting tR again allows reading the selected page. The sequential row read operation is terminated by bringing CE high.
The way the Read1 and Read2 commands work is like a pointer set to either the main area or the spare area (Refer to
Figure 19) . Writing the Read2 command user may selectively access the spare area of bytes 512 to 527. Addresses A0 to
A3 set the starting address of the spare area while addresses A4 to A7 are ignored.
Unless the operation is aborted, the page address is automatically incremented for sequential row
Read as in Read1 operation and spare sixteen bytes of each page may be sequentially read. The Read1 command (00h/
01h) is needed to move the pointer back to the main area. Figure 9 to 11 show typical sequence and timings for each read
operation.
3.2 Page Program.
The device is programmed basically on a page basis, but it does allow multiple partial page programming of a byte or
consecutive bytes up to 528, in a single page program cycle. The number of consecutive partial page programming oper-
ations within the same page without an intervening erase operation must not exceed 1 for main array and 2 for spare
array. The addressing may be done in any random order in a block. A page program cycle consists of a serial data loading
period in which up to 528 bytes of data may be loaded into the page register, followed by a non-volatile programming
period where the loaded data is programmed into the appropriate cell. Serial data loading can be started from 2nd half
array by moving pointer. About the pointer operation, please refer to Figure 20.
The data-loading sequence begins by inputting the Serial Data Input command (80h), followed by the four address input
cycles (Refer to Table 3 for details) and then serial data loading. The Page Program confirm command (10h) starts the
programming process. Writing 10h alone without previously entering the serial data will not initiate the programming proc-
ess. The internal Program Erase Controller automatically executes the algorithms and timings necessary for program and
verify, thereby freeing the system controller for other tasks. Once the program process starts, the Read Status Register
command may be entered, with RE and CE low, to read the status register. The system controller can detect the completion
of a program cycle by monitoring the R/B output, or the Status bit (I/O 6) of the Status Register. Only the Read Status
command and Reset command are valid while programming is in progress. When the Page Program is complete, the Write
Status Bit (I/O 0) may be checked as specified in Figure 12.
The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register
remains in Read Status command mode until another valid command is written to the command register.
Rev 1.0 / Dec. 2008
11
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