PDF H27U1G8F2B Data sheet ( Hoja de datos )

Número de pieza	H27U1G8F2B
Descripción	1 Gbit (128 M x 8 bit) NAND Flash
Fabricantes	Hynix
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No Preview Available ! 1 H27U1G8F2B Series 1 Gbit (128 M x 8 bit) NAND Flash 1 Gb NAND Flash H27U1G8F2B This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 1.2 / Dec. 2009 1 1 page VCC CE IO0~IO7 WE RE R/B ALE CLE WP VSS Figure 1 : Logic Diagram 1 H27U1G8F2B Series 1 Gbit (128 M x 8 bit) NAND Flash IO7 - IO0 CLE ALE CE RE WE WP R/B Vcc Vss NC Data Input / Outputs Command latch enable Address latch enable Chip Enable Read Enable Write Enable Write Protect Ready / Busy Power Supply Ground No Connection Table 1 : Signal Names 1& 1& 1& 1& 1& 1& 5% 5( &( 1& 1& 9FF 9VV 1& 1& &/( $/( :( :3 1& 1& 1& 1& 1& 1$1')ODVK 7623 [ 1& 1& 1& 1& ,2 ,2 ,2 ,2 1& 1& 1& 9FF 9VV 1& 1& 1& ,2 ,2 ,2 ,2 1& 1& 1& 1& 1 2 3 4 5 6 7 8 9 10 A NC NC B NC uhukGm GGGGGminh GGGGGGO_P NC NC NC NC C WP ALE Vss CE WE RB D NC RE CLE NC NC NC E NC NC NC NC NC NC F NC NC NC NC NC NC G NC NC NC NC NC PRE H NC I/O0 NC NC NC Vcc J NC I/O1 NC Vcc I/O5 I/O7 K Vss I/O2 I/O3 I/O4 I/O6 Vss L NC NC M NC NC NC NC NC NC Figure 2 : 48-TSOP1 / 63-FBGA Contact, x8 Device Rev 1.2 / Dec. 2009 5 5 Page 1 H27U1G8F2B Series 1 Gbit (128 M x 8 bit) NAND Flash 3.3 Block Erase. The Erase operation is done on a block basis. Block address loading is accomplished in two cycles initiated by an Erase Setup command (60h). Only address A18 to A27 is valid while A12 to A17 are ignored. The Erase Confirm command (D0h) following the block address loading initiates the internal erasing process. This two-step sequence of setup followed by ex- ecution command ensures that memory contents are not accidentally erased due to external noise conditions. At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase- verify. Once the erase process starts, the Read Status Register command may be entered to read the status register. The system controller can detect the completion of an erase by monitoring the R/B output, or the Status bit (I/O 6) of the Status Reg- ister. Only the Read Status command and Reset command are valid while erasing is in progress. When the erase operation is completed, the Write Status Bit (I/O 0) may be checked. Figure 18 details the sequence. 3.4 Copy-Back Program. The copy-back program is configured to quickly and efficiently rewrite data stored in one page without utilizing an ex- ternal memory. Since the time-consuming cycles of serial access and re-loading cycles are removed, the system perform- ance is improved. The benefit is especially obvious when a portion of a block is updated and the rest of the block is also needed to be copied to the newly assigned free block. The operation for performing a copy-back program is a sequential execution of page-read without serial access and copying-program with the address of destination page. A read operation with "35h" command and the address of the source page moves the whole 2112byte data into the internal data buffer. As soon as the device returns to Ready state, optional data read-out is allowed by toggling RE, or Copy Back command (85h) with the address cycles of destination page may be written. The Program Confirm command (10h) is required to actually begin the programming operation. Data input cycle for modifying a portion or multiple distant portions of the source page is allowed as shown in Figure 17. "When there is a program-failure at Copy-Back operation, error is reported by pass/fail status. But, if Copy-Back opera- tions are accumulated over time, bit error due to charge loss is not checked by external error detection/correction scheme. For this reason, two bit error correction is recommended for the use of Copy-Back operation." Figure 16 and Figure 17 show the command sequence for the copy-back operation. Please note that WP value is don't care during Read for copy back, while it must be set to Vcc when performing the program . 3.5 Read Status Register. The device contains a Status Register which may be read to find out whether read, program or erase operation is com- pleted, and whether the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE does not need to be toggled for updated status. Refer to Table 13 for specific Status Register definitions, and Figure 10 for specific timings requirements. The command register remains in Sta- tus Read mode until further commands are issued to it. Therefore, if the status register is read during a random read cycle, the read command (00h) should be given before starting read cycles. 3.6 Read ID. The device contains a product identification mode, initiated by writing 90h to the command register, followed by an ad- dress input of 00h. Four read cycles sequentially output the manufacturer code (ADh), and the device code and 00h, 4th cycle ID, respectively. The command register remains in Read ID mode until further commands are issued to it. Figure 19 shows the operation sequence, while Table 14 to Table 17 explain the byte meaning. Rev 1.2 / Dec. 2009 11 11 Page

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