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PDF HB52R1289E22-A6B Data sheet ( Hoja de datos )
| Número de pieza | HB52R1289E22-A6B | |
| Descripción | 1 GB Registered SDRAM DIMM 1 GB Registered SDRAM DIMM (36 pcs of 64 M 4 Components) PC100 SDRAM | |
| Fabricantes | Elpida Memory | |
| Logotipo |  |
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HB52R1289E22-A6B/B6B
1 GB Registered SDRAM DIMM
128-Mword × 72-bit, 100 MHz Memory Bus, 2-Bank Module
(36 pcs of 64 M × 4 Components)
PC100 SDRAM
E0017H20 (Ver. 2.0)
Aug. 20, 2001 (K)
Description
The HB52R1289E22 belongs to 8-byte DIMM (Dual In-line Memory Module) family, and has been
developed as an optimized main memory solution for 8-byte processor applications. The HB52R1289E22 is a
64M × 72 × 2-bank Synchronous Dynamic RAM Module, mounted 36 pieces of 256-Mbit SDRAM
(HM5225405BTB) sealed in TCP package, 1 piece of PLL clock driver, 3 pieces register driver and 1 piece of
serial EEPROM (2-kbit) for Presence Detect (PD). An outline of the HB52R1289E22 is 168-pin socket type
package (dual lead out). Therefore, the HB52R1289E22 makes high density mounting possible without
surface mount technology. The HB52R1289E22 provides common data inputs and outputs. Decoupling
capacitors are mounted beside TCP on the module board.
Note: Do not push the cover or drop the modules in order to protect from mechanical defects, which would
be electrical defects.
Features
• Fully compatible with : JEDEC standard outline 8-byte DIMM
: Intel PCB Reference design (Rev. 1.2)
• 168-pin socket type package (dual lead out)
Outline: 133.37 mm (length) × 38.10 mm (Height) × 4.80 mm (Thickness)
Lead pitch: 1.27 mm
• 3.3 V power supply
• Clock frequency: 100 MHz (max)
• LVTTL interface
• Data bus width: × 72 ECC
• Single pulsed RAS
• 4 Banks can operates simultaneously and independently
• Burst read/write operation and burst read/single write operation capability
• Programmable burst length: 1/2/4/8
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
1 page  
HB52R1289E22-A6B/B6B
Serial PD Matrix*1
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
0 Number of bytes used by 1 0 0 0 0 0 0 0 80 128
module manufacturer
1 Total SPD memory size
0 0 0 0 1 0 0 0 08
256 byte
2 Memory type
0 0 0 0 0 1 0 0 04
SDRAM
3 Number of row addresses bits 0 0 0 0 1 1 0 1 0D 13
4 Number of column addresses 0 0 0 0 1 0 1 1 0B 11
bits
5 Number of banks
0 0 0 0 0 0 1 0 02
2
6 Module data width
0 1 0 0 1 0 0 0 48
72 bit
7 Module data width (continued) 0 0 0 0 0 0 0 0 00 0 (+)
8 Module interface signal levels 0 0 0 0 0 0 0 1 01 LVTTL
9 SDRAM cycle time
(highest CE latency)
10 ns
1 0 1 0 0 0 0 0 A0
CL = 3
10
SDRAM access from Clock
0 1 1 0 0 0 0 0 60
(highest CE latency)
6 ns
*3
11 Module configuration type
0 0 0 0 0 0 1 0 02
ECC
12 Refresh rate/type
1 0 0 0 0 0 1 0 82
Normal
(7.8125 µs)
Self refresh
13 SDRAM width
0 0 0 0 0 1 0 0 04
64M × 4
14 Error checking SDRAM width 0 0 0 0 0 1 0 0 04
×4
15 SDRAM device attributes:
0 0 0 0 0 0 0 1 01
minimum clock delay for back-to-
back random column addresses
1 CLK
16 SDRAM device attributes:
Burst lengths supported
0 0 0 0 1 1 1 1 0F
1, 2, 4, 8
17 SDRAM device attributes:
0 0 0 0 0 1 0 0 04
number of banks on SDRAM
device
4
18 SDRAM device attributes:
CE latency
(-A6B)
0 0 0 0 0 1 1 0 06
2/3
(-B6B)
0 0 0 0 0 1 0 0 04
3
19 SDRAM device attributes:
S latency
0 0 0 0 0 0 0 1 01
0
Data Sheet E0017H20
5
5 Page 
HB52R1289E22-A6B/B6B
DC Characteristics (Ta = 0 to 55°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V)
HB52R1289E22
-A6B
-B6B
Parameter
Symbol Min Max Min Max Unit Test conditions Notes
Operating current
(CE latency = 3)
I CC1
(CE latency = 4)
I CC1
Standby current in power ICC2P
down
Burst length = 1 1, 2, 3
— 2945 — — mA tRC = min
— 2945 — 2945 mA
—
803 —
803 mA
CKE = VIL, tCK = 12 6
ns
Standby current in power ICC2PS
—
767 —
767 mA
CKE = VIL, tCK = ∞ 7
down (input signal stable)
Standby current in non ICC2N
—
1415 —
1415 mA
CKE, S = VIH,
power down
tCK = 12 ns
4
Active standby current in ICC3P
power down
—
839 —
839 mA
CKE = VIL, tCK = 12 1, 2, 6
ns
Active standby current in ICC3N
non power down
Burst operating current
(CE latency = 3)
(CE latency = 4)
Refresh current
(CE latency = 3)
(CE latency = 4)
Self refresh current
I CC4
I CC4
I CC5
I CC5
I CC6
Input leakage current
Output leakage current
I LI
I LO
— 1775 — 1775 mA
— 2945 — — mA
— 2945 — 2945 mA
— 5195 — — mA
— 5195 — 5195 mA
— 803 — 803 mA
–10 10
–10 10
–10 10
–10 10
µA
µA
CKE, S = VIH,
tCK = 12 ns
tCK = min, BL = 4
1, 2, 4
1, 2, 5
tRC = min
3
VIH ≥ VCC – 0.2 V
VIL ≤ 0.2 V
0 ≤ Vin ≤ VCC
0 ≤ Vout ≤ VCC
DQ = disable
8
Output high voltage
VOH
2.4 —
2.4 —
V
IOH = –4 mA
Output low voltage
VOL — 0.4 — 0.4 V IOL = 4 mA
Notes: 1. ICC depends on output load condition when the device is selected. ICC (max) is specified at the
output open condition.
2. One bank operation.
3. Input signals are changed once per one clock.
4. Input signals are changed once per two clocks.
5. Input signals are changed once per four clocks.
6. After power down mode, CK operating current.
7. After power down mode, no CK operating current.
8. After self refresh mode set, self refresh current.
Data Sheet E0017H20
11
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