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PDF H26M11001BAR Data sheet ( Hoja de datos )
| Número de pieza | H26M11001BAR | |
| Descripción | 1GB e-NAND | |
| Fabricantes | Hynix | |
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e-NAND
1GB e-NAND
H26M11001BAR
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev 1.0 / Sep. 2009
1
1 page  
e-NAND
1.3 Flash Independent Technology
The 512 byte sector size of the Hynix e-NAND is the same as that in an IDE magnetic disk drive.
To write or read a sector (or multiple sectors), the host computer software simply issues a Read or Write command to the
e-NAND. This command contains the address and the number of sectors to write/read. The host software then waits for
the command to complete. The host software does not get involved in the details of how the flash memory is erased, pro-
grammed or read. This is extremely important as flash devices are expected to get more and more complex in the future.
Because the e-NAND uses an intelligent on-board controller, the host system software will not require changing as new
flash memory evolves.
1.4 Defect and Error Management
The Hynix e-NAND contain a sophisticated defect and error management system. This system is analogous to the systems
found in magnetic disk drives and in many cases offers enhancements. For instance, disk drives do not typically perform a
read after write to confirm the data is written correctly because of the performance penalty that would be incurred. e-
NAND do a read after write under margin conditions to verify that the data is written correctly (except in the case of a
Write without Erase Command). In the rare case that a bit is found to be defective. e-NAND will even replace the entire
sector with a spare sector. This is completely transparent to the host and does not consume any user data space. The e-
NAND soft error rate specification is much better than the magnetic disk drive specification. In the extremely rare case a
read error does occur, e-NAND have innovative algorithms to recover the data. This is similar to using retries on a disk
drive but is much more sophisticated. The last line of defense is to employ powerful ECC to correct the data. If ECC is
used to recover data, defective bits are replaced with spare bits to ensure they do not cause any future problems. These
defect and error management systems coupled with the solid-state construction give e-NAND unparalleled reliability.
1.5 Sleep Mode (CMD5)
A card may be switched between a Sleep state and a Standby state by SLEEP/AWAKE (CMD5). In the Sleep state the
power consumption of the memory device is minimized. In this state the memory device reacts only to the commands
RESET (CMD0) and SLEEP/AWAKE (CMD5). All the other commands are ignored by the memory device. The timeout for
state transitions between Standby state and Sleep state is defined in the EXT_CSD register S_A_timeout. The maximum
current consumptions during the Sleep state are defined in the EXT_CSD registers S_A_VCC and S_A_VCCQ.
Sleep command: The bit 15 as set to 1 in SLEEP/AWAKE (CMD5) argument.
Awake command: The bit 15 as set to 0 in SLEEP/AWAKE (CMD5) argument.
The Sleep command is used to initiate the state transition from Standby state to Sleep state. The memory device indicates
the transition phase busy by pulling down the DAT0 line. No further commands should be sent during the busy. The Sleep
state is reached when the memory device stops pulling down the DAT0 line.
The Awake command is used to initiate the transition from Sleep state to Standby state. The memory device indicates the
transition phase busy by pulling down the DAT0 line. No further commands should be sent during the busy. The Standby
state is reached when the memory device stops pulling down the DAT0 line.
During the Sleep state the Vcc power supply may be switched off. This is to enable even further system power consump-
tion saving. The Vcc supply is allowed to be switched off only after the Sleep state has been reached (the memory device
has stopped to pull down the DAT0 line). The Vcc supply have to be ramped back up at least to the min operating voltage
level before the state transition from Sleep state to Standby state is allowed to be initiated (Awake command).
Rev 1.0 / Sep. 2009
5
5 Page 
e-NAND
Pins
M5
M6
E7, G5, H10, K8
C4, N2, N5, P4, P6
C6, M4, N4, P3, P5
E6, F5, J10, K9
A3
A4
A5
B2
B3
B4
B5
B6
C2
NC
DNU
Name
CMD
CLK
Vss
Vssq
Vccq
Vcc
DATA0
DAT1
DAT2
DAT3
DAT4
DAT5
DAT6
DAT7
VDDi
MMC Interface
IO Type(1)
I/O/PP/OD
I
S
S
S
S
I/O/PP
I/O/PP
I/O/PP
I/O/PP
I/O/PP
I/O/PP
I/O/PP
I/O/PP
-
Not Connected
Do Not Use
Description
Command / Response
Clock
Flash Memory Supply Voltage
Ground
Core Supply Voltage Ground
Core Supply Voltage
Flash Memory Supply Voltage
Data
Data
Data
Data
Data
Data
Data
Data
The capacitor (0.1㎌) must be
connected for internal power
stability.
Table 3-1 : Pin Description
Note:
1. S: Power Supply; I: input; O: output; PP: push-pull; OD: open-drain;
2. The DAT0-DAT7 pins for read-only cards are output only
Rev 1.0 / Sep. 2009
11
11 Page | ||
| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet H26M11001BAR.PDF ] | |
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