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PDF HB52RF1289E2 Data sheet ( Hoja de datos )
| Número de pieza | HB52RF1289E2 | |
| Descripción | 1 GB Registered SDRAM DIMM 128-Mword 72-bit/ 133 MHz Memory Bus/ 2-Bank Module (36 pcs of 64 M 4 Components) PC133 SDRAM | |
| Fabricantes | Elpida Memory | |
| Logotipo |  |
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HB52RF1289E2-75B
1 GB Registered SDRAM DIMM
128-Mword × 72-bit, 133 MHz Memory Bus, 2-Bank Module
(36 pcs of 64 M × 4 Components)
PC133 SDRAM
E0018H20 (Ver. 2.0)
Aug. 20, 2001 (K)
Description
The HB52RF1289E2 belongs to 8-byte DIMM (Dual In-line Memory Module) family, and has been
developed as an optimized main memory solution for 8-byte processor applications. The HB52RF1289E2 is
a 64M × 72 × 2-bank Synchronous Dynamic RAM Module, mounted 36 pieces of 256-Mbit SDRAM
(HM5225405BTB) sealed in TCP package, 1 piece of PLL clock driver, 3 pieces register driver and 1 piece of
serial EEPROM (2-kbit) for Presence Detect (PD). An outline of the HB52RF1289E2 is 168-pin socket type
package (dual lead out). Therefore, the HB52RF1289E2 makes high density mounting possible without
surface mount technology. The HB52RF1289E2 provides common data inputs and outputs. Decoupling
capacitors are mounted beside TCP on the module board.
Note: Do not push the cover or drop the modules in order to protect from mechanical defects, which would
be electrical defects.
Features
• Fully compatible with : JEDEC standard outline 8-byte DIMM
• 168-pin socket type package (dual lead out)
Outline: 133.37 mm (length) × 38.10 mm (Height) × 4.80 mm (Thickness)
Lead pitch: 1.27 mm
• 3.3 V power supply
• Clock frequency: 133 MHz (max)
• LVTTL interface
• Data bus width: × 72ECC
• Single pulsed RAS
• 4 Banks can operates simultaneously and independently
• Burst read/write operation and burst read/single write operation capability
• Programmable burst length: 1/2/4/8
• 2 variations of burst sequence
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
1 page  
HB52RF1289E2-75B
Serial PD Matrix*1
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
0 Number of bytes used by 1 0 0 0 0 0 0 0 80 128
module manufacturer
1 Total SPD memory size
0 0 0 0 1 0 0 0 08
256 byte
2 Memory type
0 0 0 0 0 1 0 0 04
SDRAM
3 Number of row addresses bits 0 0 0 0 1 1 0 1 0D 13
4 Number of column addresses 0 0 0 0 1 0 1 1 0B 11
bits
5 Number of banks
0 0 0 0 0 0 1 0 02
2
6 Module data width
0 1 0 0 1 0 0 0 48
72 bit
7 Module data width (continued) 0 0 0 0 0 0 0 0 00 0 (+)
8 Module interface signal levels 0 0 0 0 0 0 0 1 01 LVTTL
9 SDRAM cycle time
(highest CE latency)
7.5 ns
0 1 1 1 0 1 0 1 75
CL = 3
10
SDRAM access from Clock
0 1 0 1 0 1 0 0 54
(highest CE latency)
5.4 ns
*5
11 Module configuration type
0 0 0 0 0 0 1 0 02
ECC
12 Refresh rate/type
1 0 0 0 0 0 1 0 82
Normal
(7.8125 µs)
Self refresh
13 SDRAM width
0 0 0 0 0 1 0 0 04
64M × 4
14 Error checking SDRAM width 0 0 0 0 0 1 0 0 04
×4
15 SDRAM device attributes:
0 0 0 0 0 0 0 1 01
minimum clock delay for back-to-
back random column addresses
1 CLK
16 SDRAM device attributes:
Burst lengths supported
0 0 0 0 1 1 1 1 0F
1, 2, 4, 8
17 SDRAM device attributes:
0 0 0 0 0 1 0 0 04
number of banks on SDRAM
device
4
18 SDRAM device attributes:
CE latency
0 0 0 0 0 1 1 0 06
2/3
19 SDRAM device attributes:
S latency
0 0 0 0 0 0 0 1 01
0
Data Sheet E0018H10
5
5 Page 
HB52RF1289E2-75B
Capacitance (Ta = 25°C, VCC = 3.3 V ± 0.3 V)
Parameter
Symbol
Max
Unit
Notes
Input capacitance (Address)
CI1 25 pF 1, 2, 4
Input capacitance (RE, CE, W)
CI2 25 pF 1, 2, 4
Input capacitance (CKE)
CI3 45 pF 1, 2, 4
Input capacitance (S)
CI4 20 pF 1, 2, 4
Input capacitance (CK)
CI5 45 pF 1, 2, 4
Input capacitance (DQMB)
CI6 20 pF 1, 2, 4
Input/Output capacitance (DQ)
CI/O1
25
pF
1, 2, 3, 4
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. Measurement condition: f = 1 MHz, 1.4 V bias, 200 mV swing.
3. DQMB = VIH to disable Data-out.
4. This parameter is sampled and not 100% tested.
AC Characteristics (Ta = 0 to 55°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V)
Parameter
System clock cycle time
CK high pulse width
CK low pulse width
Access time from CK
Data-out hold time
CK to Data-out low impedance
CK to Data-out high impedance
Data-in setup time
Data in hold time
Address setup time
Address hold time
CKE setup time
CKE setup time for power down exit
CKE hold time
HB52RF1289E2-75B
PC133
PC100
CE latency = 4 CE latency = 3
PC100
Symbol Symbol Min
Max Min
Max
t CK
Tclk 7.5
—
10
—
t CKH
Tch 3.4
—
4
—
tCKL Tcl 3.4 — 4
—
t AC
Tac —
6.3 —
6.9
t OH
Toh 1.8
—
2.1 —
t LZ
1.1 —
1.1 —
tHZ — 6.3 — 6.9
t DS
Tsi 2.4 —
2.9 —
t DH
Thi 1.7 —
1.9 —
t AS
Tsi 1.9 —
2.6 —
t AH
Thi 1.5 —
1.6 —
tCES Tsi 1.9 — 2.6 —
t CESP
Tpde 1.9
—
2.6 —
tCEH Thi 1.5 — 1.6 —
Unit Notes
ns 1
ns 1
ns 1
ns 1, 2
ns 1, 2
ns 1, 2, 3
ns 1, 4
ns 1
ns 1
ns 1
ns 1
ns 1, 5
ns 1
ns 1
Data Sheet E0018H10
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet HB52RF1289E2.PDF ] | |
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