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PDF HB54A2568KN Data sheet ( Hoja de datos )
| Número de pieza | HB54A2568KN | |
| Descripción | 256MB DDR SDRAM S.O.DIMM | |
| Fabricantes | Elpida Memory | |
| Logotipo |  |
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PRELIMINARY DATA SHEET
256MB DDR SDRAM S.O.DIMM
HB54A2568KN-A75B/B75B/10B (32M words × 64 bits, 2 Banks)
Description
Features
The HB54A2568KN is Double Data Rate (DDR)
SDRAM Module, mounted 256M bits DDR SDRAM
(HM5425161BTT) sealed in TSOP package, and 1
piece of serial EEPROM (2k bits EEPROM) for
Presence Detect (PD). The HB54A2568KN is
organized as 16M × 64 × 2 bank mounted 8 pieces of
256M bits DDR SDRAM. Read and write operations
are performed at the cross points of the CK and the
/CK. This high-speed data transfer is realized by the 2
bits prefetch-pipelined architecture. Data strobe (DQS)
both for read and write are available for high speed and
reliable data bus design. By setting extended mode
register, the on-chip Delay Locked Loop (DLL) can be
set enable or disable. An outline of the products is
200-pin socket type package (dual lead out).
Therefore, it makes high density mounting possible
without surface mount technology. It provides common
data inputs and outputs. Decoupling capacitors are
mounted beside each TSOP on the module board.
• 200-pin socket type package (dual lead out)
Outline: 67.6mm (Length) × 31.75mm (Height) ×
3.80mm (Thickness)
Lead pitch: 0.6mm
• 2.5V power supply (VCC)
• SSTL-2 interface for all inputs and outputs
• Clock frequency: 133 MHz (max) (-A75B/B75B)
: 100 MHz (max) (-10B)
• Data inputs, outputs and DM are synchronized with
DQS
• 4 banks can operate simultaneously and
independently (Component)
• Burst read/write operation
• Programmable burst length: 2, 4, 8
Burst read stop capability
• Programmable burst sequence
Sequential
Interleave
• Start addressing capability
Even and Odd
• Programmable /CAS latency (CL): 2, 2.5
• 8192 refresh cycles: 7.8µs (8192row /64ms)
• 2 variations of refresh
Auto refresh
Self refresh
Document No. E0148H20 (Ver. 2.0)
Date Published April 2002 (K) Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2001-2002
Hitachi, Ltd. 2001
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
1 page  
HB54A2568KN-A75B/B75B/10B
Serial PD Matrix*1
Byte No.
0
1
2
3
4
5
6
7
8
9
10
11
Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
Number of bytes utilized by module
manufacturer
1
0
0
0
0
0
0
0
80
Total number of bytes in serial PD
device
0 0 0 0 1 0 0 0 08
Memory type
0 0 0 0 0 1 1 1 07
Number of row address
0 0 0 0 1 1 0 1 0D
Number of column address
0 0 0 0 1 0 0 1 09
Number of DIMM banks
0 0 0 0 0 0 1 0 02
Module data width
0 1 0 0 0 0 0 0 40
Module data width continuation
0 0 0 0 0 0 0 0 00
Voltage interface level of this assembly 0 0 0 0 0 1 0 0 04
DDR SDRAM cycle time, CL = X
-A75B
0 1 1 1 0 0 0 0 70
-B75B
0 1 1 1 0 1 0 1 75
-10B
SDRAM access from clock (tAC)
-A75B/B75B
-10B
1 0 0 0 0 0 0 0 80
0 1 1 1 0 0 0 0 70
1 0 0 0 0 0 0 0 80
DIMM configuration type
0 0 0 0 0 0 0 0 00
12 Refresh rate/type
1 0 0 0 0 0 1 0 82
13 Primary SDRAM width
0 0 0 1 0 0 0 0 10
14 Error checking SDRAM width
0 0 0 0 0 0 0 0 00
SDRAM device attributes:
15 Minimum clock delay back-to-back 0 0 0 0 0 0 0 1 01
column access
16
SDRAM device attributes:
Burst length supported
0 0 0 0 1 1 1 0 0E
17
SDRAM device attributes: Number of
banks on SDRAM device
0
0
0
0
0
1
0
0
04
18
SDRAM device attributes:
/CAS latency
0 0 0 0 1 1 0 0 0C
19
SDRAM device attributes:
/CS latency
0 0 0 0 0 0 0 1 01
20
SDRAM device attributes:
/WE latency
0 0 0 0 0 0 1 0 02
21 SDRAM module attributes
0 0 1 0 0 0 0 0 20
22 SDRAM device attributes: General 1 0 0 0 0 0 0 0 80
Minimum clock cycle time at
23 CLX - 0.5
-A75B
0 1 1 1 0 1 0 1 75
-B75B/10B
1 0 1 0 0 0 0 0 A0
Maximum data access time (tAC) from
24 clock at CLX - 0.5
0 1 1 1 0 0 0 0 70
-A75B/B75B
-10B
1 0 0 0 0 0 0 0 80
25
Minimum clock cycle time at
CLX - 1
0 0 0 0 0 0 0 0 00
26
Maximum data access time (tAC) from
clock at CLX - 1
0
0
0
0
0
0
0
0
00
27 Minimum row precharge time (tRP) 0 1 0 1 0 0 0 0 50
Comments
128
256 byte
SDRAM DDR
13
9
2
64 bits
0 (+)
SSTL 2.5V
CL = 2.5*5
0.7ns*5
0.8ns*5
Non-parity
7.8 µs
Self refresh
× 16
Not used
1 CLK
2, 4, 8
4
2, 2.5
0
1
Unbuffered
± 0.2V
CL = 2*5
0.7ns*5
0.8ns*5
20ns
Preliminary Data Sheet E0148H20 (Ver. 2.0)
5
5 Page 
HB54A2568KN-A75B/B75B/10B
Pin Functions (1)
CK (CLK), /CK (/CLK) (input pin): The CK and the /CK are the master clock inputs. All inputs except DMs, DQSs
and DQs are referred to the cross point of the CK rising edge and the VREF level. When a read operation, DQSs
and DQs are referred to the cross point of the CK and the /CK. When a write operation, DMs and DQs are referred
to the cross point of the DQS and the VREF level. DQSs for write operation are referred to the cross point of the CK
and the /CK.
/S (/CS) (input pin): When /S is Low, commands and data can be input. When /S is High, all inputs are ignored.
However, internal operations (bank active, burst operations, etc.) are held.
/RAS, /CAS, and /WE (input pins): These pins define operating commands (read, write, etc.) depending on the
combinations of their voltage levels. See "Command operation".
A0 to A12 (input pins): Row address (AX0 to AX12) is determined by the A0 to the A12 level at the cross point of
the CK rising edge and the VREF level in a bank active command cycle. Column address (AY0 to AY8) is loaded via
the A0 to the A8 at the cross point of the CK rising edge and the VREF level in a read or a write command cycle.
This column address becomes the starting address of a burst operation.
A10 (AP) (input pin): A10 defines the precharge mode when a precharge command, a read command or a write
command is issued. If A10 = High when a precharge command is issued, all banks are precharged. If A10 = Low
when a precharge command is issued, only the bank that is selected by BA1, BA0 is precharged. If A10 = High
when read or write command, auto-precharge function is enabled. While A10 = Low, auto-precharge function is
disabled.
BA0, BA1 (input pin): BA0/BA1 are bank select signals. The memory array is divided into bank 0, bank 1, bank 2
and bank 3. If BA1 = Low and BA0 = Low, bank 0 is selected. If BA1 = High and BA0 = Low, bank 1 is selected. If
BA1 = Low and BA0 = High, bank 2 is selected. If BA1 = High and BA0 = High, bank 3 is selected.
CKE (input pin): CKE controls power down and self-refresh. The power down and the self-refresh commands are
entered when the CKE is driven Low and exited when it resumes to High.
The CKE level must be kept for 1 CK cycle (= LCKEPW) at least, that is, if CKE changes at the cross point of the CK
rising edge and the VREF level with proper setup time tIS, at the next CK rising edge CKE level must be kept with
proper hold time tIH.
Pin Functions (2)
DQ (input and output pins): Data are input to and output from these pins.
DQS (input and output pin): DQS provide the read data strobes (as output) and the write data strobes (as input).
DM (input pins): DM is the reference signal of the data input mask function. DMs are sampled at the cross point of
DQS and VREF
VCC and VCCQ (power supply pins): 2.5V is applied. (VCC is for the internal circuit and VCCQ is for the output
buffer.)
VCCSPD (power supply pin): 2.5V is applied (For serial EEPROM).
VSS (power supply pin): Ground is connected.
Detailed Operation Part, AC Characteristics and Timing Waveforms
Refer to the HM5425161B/HM5425801B/HM5425401B Series datasheet (E0086H).
Preliminary Data Sheet E0148H20 (Ver. 2.0)
11
11 Page | ||
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