HB54R1G9F2-B75B Datasheet PDF - Elpida Memory
| Part Number | HB54R1G9F2-B75B | |
| Description | 1GB Registered DDR SDRAM DIMM | |
| Manufacturers | Elpida Memory | |
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DATA SHEET
1GB Registered DDR SDRAM DIMM
HB54R1G9F2-A75B/B75B/10B (128M words × 72 bits, 2 Banks)
Description
Features
The HB54R1G9F2 is a 128M × 72 × 2 bank Double
Data Rate (DDR) SDRAM Module, mounted 36 pieces
of 256Mbits DDR SDRAM (HM5425401BTB) sealed in
TCP package, 1 piece of PLL clock driver, 2 pieces of
register driver and 1 piece of serial EEPROM (2k bits
EEPROM) for Presence Detect (PD). Read and write
operations are performed at the cross points of the CK
and the /CK. This high-speed data transfer is realized
by the 2-bit prefetch-pipelined architecture. Data
strobe (DQS) both for read and write are available for
high speed and reliable data bus design. By setting
extended mode register, the on-chip Delay Locked
Loop (DLL) can be set enable or disable. An outline of
the products is 184-pin socket type package (dual lead
out). Therefore, it makes high density mounting
possible without surface mount technology. It provides
common data inputs and outputs. Decoupling
capacitors are mounted beside each TCP on the
module board.
Note: Do not push the cover or drop the modules in
order to protect from mechanical defects, which
would be electrical defects.
• 184-pin socket type package (dual lead out)
Outline: 133.35mm (Length) × 43.18mm (Height) ×
4.80mm (Thickness)
Lead pitch: 1.27mm
• 2.5V power supply (VCC/VCCQ)
• SSTL-2 interface for all inputs and outputs
• Clock frequency: 143MHz/133MHz/125MHz (max.)
• Data inputs and outputs are synchronized with DQS
• 4 banks can operate simultaneously and
independently (Component)
• Burst read/write operation
• Programmable burst length: 2, 4, 8
Burst read stop capability
• Programmable burst sequence
Sequential
Interleave
• Start addressing capability
Even and Odd
• Programmable /CAS latency (CL): 3, 3.5
• 8192 refresh cycles: 7.8µs (8192/64ms)
• 2 variations of refresh
Auto refresh
Self refresh
Document No. E0089H40 (Ver. 4.0)
Date Published August 2002 (K) Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2001-2002
Hitachi, Ltd. 2000
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
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HB54R1G9F2-A75B/B75B/10B
Serial PD Matrix*1
Byte No.
0
1
2
3
4
5
6
7
8
9
10
11
Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
Number of bytes utilized by module
manufacturer
1
0
0
0
0
0
0
0
80
Total number of bytes in serial PD
device
0 0 0 0 1 0 0 0 08
Memory type
0 0 0 0 0 1 1 1 07
Number of row address
0 0 0 0 1 1 0 1 0D
Number of column address
0 0 0 0 1 0 1 1 0B
Number of DIMM banks
0 0 0 0 0 0 1 0 02
Module data width
0 1 0 0 1 0 0 0 48
Module data width continuation
0 0 0 0 0 0 0 0 00
Voltage interface level of this assembly 0 0 0 0 0 1 0 0 04
DDR SDRAM cycle time, CL = X
-A75B
0 1 1 1 0 0 0 0 70
-B75B
0 1 1 1 0 1 0 1 75
-10B
1 0 0 0 0 0 0 0 80
SDRAM access from clock (tAC)
-A75B/B75B
-10B
0 1 1 1 0 1 0 1 75
1 0 0 0 0 0 0 0 80
DIMM configuration type
0 0 0 0 0 0 1 0 02
12 Refresh rate/type
1 0 0 0 0 0 1 0 82
13 Primary SDRAM width
0 0 0 0 0 1 0 0 04
14 Error checking SDRAM width
0 0 0 0 0 1 0 0 04
SDRAM device attributes:
15 Minimum clock delay back-to-back 0 0 0 0 0 0 0 1 01
column access
16
SDRAM device attributes:
Burst length supported
0 0 0 0 1 1 1 0 0E
17
SDRAM device attributes: Number of
banks on SDRAM device
0
0
0
0
0
1
0
0
04
18
SDRAM device attributes:
/CAS latency
19
SDRAM device attributes:
/CS latency
0 0 0 0 1 1 0 0 0C
0 0 0 0 0 0 0 1 01
20
SDRAM device attributes:
/WE latency
0 0 0 0 0 0 1 0 02
21 SDRAM module attributes
0 0 1 0 0 1 1 0 26
22 SDRAM device attributes: General 1 1 0 0 0 0 0 0 C0
Minimum clock cycle time at
23 CLX - 0.5
-A75B
0 1 1 1 0 1 0 1 75
-B75B/10B
1 0 1 0 0 0 0 0 A0
Maximum data access time (tAC) from
24 clock at CLX - 0.5
0 1 1 1 0 1 0 1 75
-A75B/B75B
-10B
1 0 0 0 0 0 0 0 80
25
Minimum clock cycle time at
CLX - 1
0 0 0 0 0 0 0 0 00
26
Maximum data access time (tAC) from
clock at CLX - 1
0
0
0
0
0
0
0
0
00
27 Minimum row precharge time (tRP) 0 1 0 1 0 0 0 0 50
Comments
128
256 byte
SDRAM DDR
13
11
2
72 bits
0 (+)
SSTL 2.5V
CL = 2.5*5
0.75ns*5
0.8ns*5
ECC
7.8 µs
Self refresh
×4
×4
1 CLK
2, 4, 8
4
2, 2.5
0
1
Registered
± 0.2V
CL = 2*5
0.75ns*5
0.8ns*5
20ns
Data Sheet E0089H40 (Ver. 4.0)
5
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for HB54R1G9F2-B75B electronic component. |
| Information | Total 16 Pages | |
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