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PDF HB56SW3272ESK Data sheet ( Hoja de datos )
| Número de pieza | HB56SW3272ESK | |
| Descripción | 256MB Buffered EDO DRAM DIMM 32-Mword x 72-bit/ 4k Refresh/ 2 Bank Module(36 pcs of 16M x 4 components) | |
| Fabricantes | Hitachi Semiconductor | |
| Logotipo |  |
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HB56SW3272ESK-5/6
256MB Buffered EDO DRAM DIMM
32-Mword × 72-bit, 4k Refresh, 2 Bank Module
(36 pcs of 16M × 4 components)
ADE-203-872B (Z)
Rev. 1.0
June 23, 1998
Description
The HB56SW3272ESK belong to 8-byte DIMM (Dual in-line Memory Module) family , and have been
developed an optimized main memory solution for 4 and 8-byte processor applications. The
HB56SW3272ESK is 32 M × 72 Dynamic RAM Module, mounted 36 pieces of 64-Mbit DRAM
(HM5165405) sealed in TCP package and 2 pieces of 16-bit BiCMOS line driver sealed in TSSOP
package. The HB56SW3272ESK offer Extended Data Out (EDO) Page Mode as a high speed access
mode. An outline of the HB56SW3272ESK are 168-pin socket type package (dual lead out). Therefore, the
HB56SW3272ESK make high density mounting possible without surface mount technology. The
HB56SW3272ESK provide common data inputs and outputs. Decoupling capacitors are mounted beside
each TCP on its module board.
Note: Do not push the cover or drop the modules in order to protect from mechanical defects, which
would be electrical defects.
Features
• 168-pin socket type package (Dual lead out)
Lead pitch : 1.27 mm
• Single 3.3 V supply (±0.3 V)
• High speed
Access time: tRAC = 50 ns/60 ns (max)
Access time: tCAC = 18 ns/20 ns (max)
• Low power dissipation
Active mode: 8.78 W/7.49 W (max)
Standby mode (TTL): 295.2 mW (max)
• JEDEC standard outline buffered 8-byte DIMM
• Buffered input except RAS and DQ
1 page  
HB56SW3272ESK-5/6
Presence Detect Pin Assignment (Controlled by PDE pin)
PDE = Low
Pin name
Pin No.
50 ns
60ns
PD1 79 1 1
PD2
163 0
0
PD3 80 0 0
PD4
164 0
0
PD5 81 1 1
PD6
165 0
1
PD7 82 0 1
PD8
166 0
0
Note: 1: High level (driver output). 0: Low level (driver output)
PDE = High
All
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
5
5 Page 
Read-Modify-Write Cycle
Parameter
Read-modify-write cycle time
RAS to WE delay time
CAS to WE delay time
Column address to WE delay time
OE hold time from WE
HB56SW3272ESK-5/6
50 ns
Symbol Min
t RWC
t RWD
t CWD
t AWD
t OEH
116
72
30
42
13
Max
—
—
—
—
—
60 ns
Min
140
84
34
49
15
Max
—
—
—
—
—
Unit Notes
ns
ns 14
ns 14
ns 14
ns
Refresh Cycle
Parameter
CAS setup time (CBR refresh cycle)
CAS hold time (CBR refresh cycle)
WE setup time (CBR refresh cycle)
WE hold time (CBR refresh cycle)
RAS precharge to CAS hold time
50 ns
Symbol Min
t CSR
t CHR
t WRP
t WRH
t RPC
10
8
5
10
5
Max
—
—
—
—
—
60 ns
Min
10
10
5
10
5
Max
—
—
—
—
—
Unit Notes
ns
ns
ns
ns
ns
EDO Page Mode Cycle
Parameter
EDO page mode cycle time
EDO page mode RAS pulse width
Access time from CAS precharge
RAS hold time from CAS precharge
Output data hold time from CAS low
CAS hold time referred OE
CAS to OE setup time
Read command hold time from CAS
precharge
Write pulse width during CAS precharge
OE precharge time
50 ns
Symbol Min
t HPC
t RASP
t CPA
t CPRH
t DOH
t COL
t COP
t RCHC
20
—
—
33
3
8
5
28
t WPE
t OEP
8
8
60 ns
Max Min
— 25
100000 —
33 —
— 40
—3
— 10
—5
— 35
— 10
— 10
Max Unit
— ns
100000 ns
40 ns
— ns
— ns
— ns
— ns
— ns
Notes
20
16
9, 17
9, 22
— ns
— ns
11
11 Page | ||
| Páginas | Total 29 Páginas | |
| PDF Descargar | [ Datasheet HB56SW3272ESK.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| HB56SW3272ESK | 256MB Buffered EDO DRAM DIMM 32-Mword x 72-bit/ 4k Refresh/ 2 Bank Module(36 pcs of 16M x 4 components) | Hitachi Semiconductor |
| HB56SW3272ESK-5 | 256MB Buffered EDO DRAM DIMM 32-Mword x 72-bit/ 4k Refresh/ 2 Bank Module(36 pcs of 16M x 4 components) | Hitachi Semiconductor |
| HB56SW3272ESK-6 | 256MB Buffered EDO DRAM DIMM 32-Mword x 72-bit/ 4k Refresh/ 2 Bank Module(36 pcs of 16M x 4 components) | Hitachi Semiconductor |
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