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AS28F128J3A Datasheet Download - Austin Semiconductor

Номер произв AS28F128J3A
Описание x8 and x16 Q-FLASH Memory
Производители Austin Semiconductor
логотип Austin Semiconductor логотип 



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AS28F128J3A Даташит, Описание, Даташиты
AUSTIN SEMICONDUCTOR, INC.
Austin Semiconductor, Inc.
PEM
AS28F128J3A
Q-Flash
Plastic Encapsulated Microcircuit
128Mb, x8 and x16 Q-FLASH Memory
Even Sectored, Single Bit per Cell Architecture
PIN ASSIGNMENT
123 456 78
FEATURES
100% Pin and Function compatible to Intel’s MLC
Family
NOR Cell Architecture
2.7V to 3.6V VCC
2.7V to 3.6V or 5V VPEN (Programming Voltage)
Asynchronous Page Mode Reads
Manufacturer’s ID Code:
9 Numonyx 0x89h
Industry Standard Pin-Out
Fully compatible TTL Input and Outputs
Common Flash Interface [CFI]
Scalable Command Set
Automatic WRITE and ERASE Algorithms
5.6us per Byte effective programming time
128 bit protection register
9 64-bit unique device identifier
9 64-bit user programmable OTP cells
Enhanced data protection feature with use of VPEN=VSS
Security OTP block feature
100,000 ERASE cycles per BLOCK
Automatic Suspend Options:
9 Block ERASE SUSPEND-to-READ
9 Block ERASE SUSPEND-to-PROGRAM
9 PROGRAM SUSPEND-to-READ
Available Operating Ranges:
9 Enhanced
[-ET] -40oC to +105oC
9 Mil-Temperature [-XT] -55oC to +125oC
For in-depth functional product detail and Timing
Diagrams, please reference Numonyx’s full product
Datasheet:
EMBEDDED FLASH MEMORY(J3vD)
Dated: December 2007
A22
CE1
A21
A20
A19
A18
A17
A16
VCC
A15
A14
A13
A12
CE0
VPEN
RP\
A11
A10
A9
A8
VSS
A7
A6
A5
A4
A3
A2
A1
A
A1 A6
B
A2 VSS
C
A3
A7
D
A4
A5
E
DQ8 DQ1
F
BYTE\ DQ0
G
A23
A0
H
CE2 DNU
A8 VPEN A13
A9 CE0 A14
A10 A12 A15
A11 RP\ DNU
DQ9 DQ3 DQ4
DQ10 DQ11 DQ12
DQ2 VCCQ DQ5
VCC VSS DQ13
VCC A18
DNU A19
DNU A20
DNU A16
DNU DQ15
DNU DNU
DQ6 DQ14
VSS DQ7
A22
CE1
A21
A17
STS
OE\
WE\
DNU
64-Ball FBGA
1 56
2 55
3 54
4 53
5 52
6 51
7 50
8 49
9 48
10 47
11 46
12 45
13 44
14 43
15 42
16 41
17 40
18 39
19 38
20 37
21 36
22 35
23 34
24 33
25 32
26 31
27 30
28 29
NC
WE\
OE\
STS
DQ15
DQ7
DQ14
DQ6
VSS
DQ13
DQ5
DQ12
DQ4
VCCQ
VSS
DQ11
DQ3
DQ10
DQ2
VCC
DQ9
DQ1
DQ8
DQ0
A0
BYTE\
A23
CE2
GENERAL DESCRIPTION
ASI’s, AS28F128J3A Enhanced or Mil-Temp variant of
Numonyx’s Q-Flash family of devices, is a nonvolatile,
electrically block-erasable (FLASH), programmable memory
device manufactured using Numonyx’s 0.15um process
technology. This device containing 134,217,728 bits organized
as either 16,777,218 (x8) or 8,388,608 bytes (x16). The device is
uniformly sectored with one hundred and twenty eight 128KB
ERASE blocks.
This device features in-system block locking. They also have
a Common FLASH Interface [CFI] that permits software
algorithms to be used for entire families of devices. The
software is device-independent, JEDEC ID-independent with
forward and backward compatibility.
AS28F128J3A
Rev. 5.5 3/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1







No Preview Available !

AS28F128J3A Даташит, Описание, Даташиты
AUSTIN SEMICONDUCTOR, INC.
Austin Semiconductor, Inc.
PEM
AS28F128J3A
Q-Flash
Functional Block Diagram:
CEx
OE\
WE\
RP\
WP\
CLK
STS
VPEN
WAIT
I/O
CNTL
Logic
ADDR
Buffer/
Latch
Power
(Current)
Control
Bus
Configuration
Register [BCR]
ADDR.
Counter
Command
Execution
Logic
[CEL]
ISM
VPP
Switch
Pump
Input
Buffer
X
Decode
128KB Memory Block (0)
128KB Memory Block (1)
128KB Memory Block (2)
128KB Memory Block (3)
Block
Erase
Control
WRITE
Buffer
128KB Memory Block (n)
Y
Dec.
Y - Select
Control
Sense Amplifiers
WRITE/ERASE Bit
Compare and
Verify
DQ0-8 or
DQ0-15
Status
Register
Identification
Register
Query
Output
Buffer
Additionally, the Scaleable Command Set [SCS] allows a single,
simple software driver in all host systems to work with all SCS
compliant FLASH memory devices. The SCS provides the
fastest system/device data transfer rates and minimizes the
device and system-level implementation costs.
VPEN serves as an input with 2.7V, 3.3V or 5V levels for
application programming. VPEN in this Q-Flash device can
provide data protection when connected to ground. This pin
also enables PROGRAM or ERASE LOCKOUT functions/
controls during power transitions.
To optimize the processor-memory interface, the device
accommodates VPEN, which is switchable during BLOCK
ERASE, PROGRAM, or LOCK BIT configurations and in
addition can be hard-wired to VCC all dependent on the end
application(s). VPEN is treated as an input pin to enable
ERASING, PROGRAMMING, and BLOCK LOCKING. When
VPEN is lower than the VCC lockout voltage (VLKO), all
program functions are disabled. BLOCK ERASE SUSPEND
mode enables the user to stop BLOCK ERASE to READ data
from or PROGRAM data to any other blocks. Similarly,
PROGRAM SUSPEND mode enables the user to SUSPEND
PROGRAMMING to READ data or execute code from any
un-suspended block(s).
This device is an even-sectored device architecture offering
individual BLOCK LOCKING that can LOCK and UN-LOCK a
block using the SECTOR LOCK BITS command sequence.
Status [STS] is a logic signal output that gives an additional
indicator of the internal state machine [ISM] activity by
providing a hardware signal of both the status and status
masking. This status indicator minimizes central processing
unit overhead and system power consumption. In the default
mode, STS acts as an RY/BY\ pin. When LOW, STS indicates
that the ISM is performing a BLOCK ERASE, PROGRAM, or
LOCK BIT configuration. When HIGH, STS indicates that the
ISM is ready for a new command.
AS28F128J3A
Rev. 5.5 3/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
2







No Preview Available !

AS28F128J3A Даташит, Описание, Даташиты
AUSTIN SEMICONDUCTOR, INC.
Austin Semiconductor, Inc.
PEM
AS28F128J3A
Q-Flash
Three Chip Enable (CEx) pins are used for enabling and
disabling the device by activating the device’s control logic,
input buffer, decoders, and sense amplifiers.
BYTE\ enables the device to be used in x8 or x16 configuration.
Byte=Low (logic 0) selects and 8-bit mode with address zero
(A0) selecting the High or Low Byte and Byte=High (logic 1)
selects the 16-bit or Word mode. When the device is in Word
mode, address one (A1) becomes the low order address bit
and address zero (A0) becomes a no-connect (NC).
RP\ is used to reset the device. When the device is disabled
and RP\ is at VCC, the STANDBY mode is enabled. A reset
time (tRWH) is required after RP\ switches to a High (logic 1)
and the outputs become valid. Likewise, the device has a wake
time (tRS) from RP\ High until WRITES to the Command User
Interface [CUI] are recognized, RESETS the ISM and clears the
status register.
Capacitance
Chip Enable Truth Table
CE2 CE1 CE0 Device
VIL VIL VIL Enabled
VIL VIL VIH Disabled
VIL VIH VIL Disabled
VIL VIH VIH Disabled
VIH VIL VIL Enabled
VIH VIL VIH Enabled
VIH VIH VIL Enabled
VIH VIH VIH Disabled
Absolute Maximum Ratings
Parameter/Condition Symbol
InputCapacitance
Cin
Typ
5
Max Units
8 pF
OutputCapacitance
Cbyte
14
16
pF
Cout 5
12 pF
Stress greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum
conditions for any duration or segment of time may affect device
reliability.
Voltage
TemperatureUnderBias
StorageTemperature
ShortCircuitCurrent
Min Max Units Notes
Ͳ55 125
oC
Ͳ65 125
oC
100 mA
1
Notes
1: All specified voltages are with respect to GND. Minimum DC
voltage is -0.5v on input/output pins and -0.2v on Vcc and VPEN
pins. During transitions, this level may undershoot to -2.0v for
periods </= 20ns. Maximum DC voltage on input/output pins,
Vcc and VPEN is VCC+0.5V which, during transitions, may
overshoot to Vcc + 2.0v for periods <20ns.
Pin Description Table
SignalName
Address
ChipEnables
WriteEnable
Symbol
A0,A1,A2,A3,A4,
A5,A6,A7,A8,A9,
A10,A11,
A12,A13,A14,A15,
A16,A17,A18,A19,
A20,A21,A22,A23
CE0,CE1,CE2
WE\
Reset/PowerDown
RP\
OutputEnable
OE\
ByteModeControl
BYTE\
ProgrammingVoltage
VPEN
StatusPin/Flag
Input/OutputVoltage
SupplyVoltage
DigitalGround
NoConnect(s)
STS
VCCQ
VCCQ
GND
NC
Type
Input
Input
Input
Input
Input
Input
Input
Output
Supply
Supply
Supply
Ͳ
Pin Description
32,28,27,26, AddressInputsduringREADandWRITEOperations.A0isonlyusedinx8
25,24,23,22, modeandwillbeaNCinx16mode.
20,19,18,17,
13,12,11,10,
8,7,6,5,
4,3,1,30
14,2,29 ThreeChipEnablepinsforMultipledevices.Seechartforfunction
55 WriteControl
Reset/PowerͲDown,WhenLowthecontrolpinresetsthestatusReg.and
16 ISMtoarrayREADmode.
OutputEnablecontrolenabledataoutputbufferswhenLow,andwhen
54 Hightheoutputbuffersaredisabled
31
ConfigurationControlpin.WhenHighthedeviceisinx16mode,when
LowthedeviceisinBytemode(x8)
NecessaryVoltagepinforProgramming,Erasingorconfiguringlockbits.
TypicallyconnectedtoVCC.WhenVPEN</=VPENLK,this
15 enablesHardwareWriteProtect.
IndicatesthestatusoftheISM.Whenconfiguredinlevelmode,STSacts
53 asaRY/BY\pin.Whenconfiguredinitspulsemode,itcan
pulsetoindicatePROGRAMandorERASEcompletion.
Separate/IsolatedVoltagesupplyforInput/Outputbus.Allows
43 voltagematchingtodifferentinterfacestandards.
9,37 PowerSupply:2.7VͲ3.6V
21,42,48 Ground
1,30,56 Noelectricalconnectionorfunction
AS28F128J3A
Rev. 5.5 3/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
3










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