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PDF AS28F128J3A Data sheet ( Hoja de datos )

Número de pieza AS28F128J3A
Descripción x8 and x16 Q-FLASH Memory
Fabricantes Austin Semiconductor 
Logotipo Austin Semiconductor Logotipo



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AUSTIN SEMICONDUCTOR, INC.
Austin Semiconductor, Inc.
PEM
AS28F128J3A
Q-Flash
Plastic Encapsulated Microcircuit
128Mb, x8 and x16 Q-FLASH Memory
Even Sectored, Single Bit per Cell Architecture
PIN ASSIGNMENT
123 456 78
FEATURES
100% Pin and Function compatible to Intel’s MLC
Family
NOR Cell Architecture
2.7V to 3.6V VCC
2.7V to 3.6V or 5V VPEN (Programming Voltage)
Asynchronous Page Mode Reads
Manufacturer’s ID Code:
9 Numonyx 0x89h
Industry Standard Pin-Out
Fully compatible TTL Input and Outputs
Common Flash Interface [CFI]
Scalable Command Set
Automatic WRITE and ERASE Algorithms
5.6us per Byte effective programming time
128 bit protection register
9 64-bit unique device identifier
9 64-bit user programmable OTP cells
Enhanced data protection feature with use of VPEN=VSS
Security OTP block feature
100,000 ERASE cycles per BLOCK
Automatic Suspend Options:
9 Block ERASE SUSPEND-to-READ
9 Block ERASE SUSPEND-to-PROGRAM
9 PROGRAM SUSPEND-to-READ
Available Operating Ranges:
9 Enhanced
[-ET] -40oC to +105oC
9 Mil-Temperature [-XT] -55oC to +125oC
For in-depth functional product detail and Timing
Diagrams, please reference Numonyx’s full product
Datasheet:
EMBEDDED FLASH MEMORY(J3vD)
Dated: December 2007
A22
CE1
A21
A20
A19
A18
A17
A16
VCC
A15
A14
A13
A12
CE0
VPEN
RP\
A11
A10
A9
A8
VSS
A7
A6
A5
A4
A3
A2
A1
A
A1 A6
B
A2 VSS
C
A3
A7
D
A4
A5
E
DQ8 DQ1
F
BYTE\ DQ0
G
A23
A0
H
CE2 DNU
A8 VPEN A13
A9 CE0 A14
A10 A12 A15
A11 RP\ DNU
DQ9 DQ3 DQ4
DQ10 DQ11 DQ12
DQ2 VCCQ DQ5
VCC VSS DQ13
VCC A18
DNU A19
DNU A20
DNU A16
DNU DQ15
DNU DNU
DQ6 DQ14
VSS DQ7
A22
CE1
A21
A17
STS
OE\
WE\
DNU
64-Ball FBGA
1 56
2 55
3 54
4 53
5 52
6 51
7 50
8 49
9 48
10 47
11 46
12 45
13 44
14 43
15 42
16 41
17 40
18 39
19 38
20 37
21 36
22 35
23 34
24 33
25 32
26 31
27 30
28 29
NC
WE\
OE\
STS
DQ15
DQ7
DQ14
DQ6
VSS
DQ13
DQ5
DQ12
DQ4
VCCQ
VSS
DQ11
DQ3
DQ10
DQ2
VCC
DQ9
DQ1
DQ8
DQ0
A0
BYTE\
A23
CE2
GENERAL DESCRIPTION
ASI’s, AS28F128J3A Enhanced or Mil-Temp variant of
Numonyx’s Q-Flash family of devices, is a nonvolatile,
electrically block-erasable (FLASH), programmable memory
device manufactured using Numonyx’s 0.15um process
technology. This device containing 134,217,728 bits organized
as either 16,777,218 (x8) or 8,388,608 bytes (x16). The device is
uniformly sectored with one hundred and twenty eight 128KB
ERASE blocks.
This device features in-system block locking. They also have
a Common FLASH Interface [CFI] that permits software
algorithms to be used for entire families of devices. The
software is device-independent, JEDEC ID-independent with
forward and backward compatibility.
AS28F128J3A
Rev. 5.5 3/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1

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AS28F128J3A pdf
AUSTIN SEMICONDUCTOR, INC.
Austin Semiconductor, Inc.
Memory Command Set Operations
PEM
AS28F128J3A
Q-Flash
Command
READARRAY
READIDENTIFIERCODES
READQUERY
READSTATUSREGISTER
CLEARSTATUSREGISTER
WRITETOBUFFER
WORD/BYTEPROGRAM
BLOCKERASE
BLOCKERASE/PROGRAMSUSPEND
BLOCKERASE/PROGRAMRESUME
CONFIGURATION
SETBLOCKLOCKBITS
CLEARBLOCKLOCKBITS
PROTECTIONPROGRAM
ScalableorBasicCommand
Set[SCSorBCS]
SCS/BCS
SCS/BCS
SCS
SCS/BCS
SCS/BCS
SCS/BCS
SCS/BCS
SCS/BCS
SCS/BCS
SCS/BCS
SCS
SCS
SCS
BusCycles
1
>/=2
2
1
>2
2
2
1
1
2
2
2
2
FirstBusCycle
Operation Address Data
WRITE
X
FFh
WRITE
X
90h
WRITE
X
98h
WRITE
X
70h
WRITE
X
50h
WRITE
BA
E8h
WRITE
X 40hor10h
WRITE
BA
20h
WRITE
X
B0h
WRITE
X
D0h
WRITE
X
B8h
WRITE
X
60h
WRITE
X
60h
WRITE
X
C0h
SecondBusCycle
Operation Address Data
READ
READ
READ
IA
QA
X
ID
QD
SRD
WRITE
WRITE
WRITE
BA
PA
BA
N
PD
D0h
WRITE
WRITE
WRITE
WRITE
X
BA
X
PA
CC
01h
D0h
PD
Notes
1
2
3,4,5
6,7
5,6
7,8
7
Key:
[IA]
[ID]
[BA]
[QA]
[PA]
[QD]
[SRD]
Notes
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
Identifier Code address
Data read from identifier Code
Address within a Block
Query data base Address
Address of Memory location to be programmed
Data read from Query data base
Data read from Status Register
Following the READ IDENTIFIER CODES command, READ operations access manufacturer, device, and block lock codes.
If the ISM is running, only DQ7 is valid; DQ15-DQ8 and DQ6-DQ0 are placed in High-Z
After the WRITE-to-BUFFER command is issued, check the XSR to make sure a buffer is available for WRITING
The number of Bytes/words to be written to the write buffer = n+1, where n=byte/word count argument. Count ranges on this device for byte
mode are n=00H to n=1Fh and for word mode, n=0000h to 000Fh. The third and consecutive bus cycles, as determined by n, are for writing data
into the write buffer. The CONFIRM command (D0h) is expected after exactly n+1 WRITE cycles; any other command at that point in the
sequence aborts the WRITE-to-BUFFER operation.
The WRITE-to-BUFFER or ERASE operation does not begin until a CONFIRM command (D0h) is issued
Attempts to issue a BLOCK ERASE or PROGRAM to a locked block will fail
Etiher 40h or 10h is recognized by the ISM as the byte/word program setup
PROGRAM SUSPEND can be issued after either the WRITE-to-BUFFER or WORD/BYTE PROGRAM operation is inititated. The CLEAR BLOCK
LOCK BITS operation simultaneously clears all block lock bits.
AS28F128J3A
Rev. 5.5 3/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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