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AS5SP128K32 Datasheet Download - Micross Components

Номер произв AS5SP128K32
Описание Synchronous SRAM
Производители Micross Components
логотип Micross Components логотип 



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AS5SP128K32 Даташит, Описание, Даташиты
SSRAM
AS5SP128K32
Plastic Encapsulated Microcircuit
4.0Mb, 128K x 32, Synchronous SRAM
Pipeline Burst, Single Cycle Deselect
FEATURES
• Synchronous Operation in relation to the input Clock
• 2 Stage Registers resulting in Pipeline operation
• On chip address counter (base +3) for Burst operations
• Self-Timed Write Cycles
• On-Chip Address and Control Registers
• Byte Write support
• Global Write support
• On-Chip low power mode [powerdown] via ZZ pin
• Interleaved or Linear Burst support via Mode pin
• Three Chip Enables for ease of depth expansion without
Data Contention.
• Two Cycle load, Single Cycle Deselect
• Asynchronous Output Enable (OE\)
• Three Pin Burst Control (ADSP\, ADSC\, ADV\)
• 3.3V Core Power Supply
• 3.3V/2.5V IO Power Supply
• JEDEC Standard 100 pin TQFP Package
• Available in Industrial, Enhanced, and Mil-Temperature
Operating Ranges
TQFP in copper lead frame for superior thermal
performance
RoHs compliant options available
NC
DQc
DQc
VDDQ
VSSQ
DQc
DQc
DQc
DQc
VSSQ
VDDQ
DQc
DQc
NC
VDD
NC
VSS
DQd
DQd
VDDQ
VSSQ
DQd
DQd
DQd
DQd
VSSQ
VDDQ
DQd
DQd
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SSRAM [SPB]
80 NC
79 DQb
78 DQb
77 VDDQ
76 VSSQ
75 DQb
74 DQb
73 DQb
72 DQb
71 VSSQ
70 VDDQ
69 DQb
68 DQb
67 VSS
66 NC
65 VDD
64 ZZ
63 DQa
62 DQa
61 VDDQ
60 VSSQ
59 DQa
58 DQa
57 DQa
56 DQa
55 VSSQ
54 VDDQ
53 DQa
52 DQa
51 NC
FAST ACCESS TIMES
Parameter
CycleTime
ClockAccessTime
OutputEnableAccessTime
Symbol 200Mhz 166Mhz 133Mhz 100Mhz Units
tCYC 5.0 6.0 7.5 10.0 ns
tCD 3.0 3.5 4.0 5.0 ns
tOE 3.0 3.5 4.0 5.0 ns
GENERAL DESCRIPTION
The AS5SP128K32 is a 4.0Mb High Performance Synchronous
BLOCK DIAGRAM
OE\
ZZ
CLK
Pipeline Burst SRAM, available in multiple temperature
screening levels, fabricated using High Performance CMOS
technology and is organized as a 128K x 32. It integrates
address and control registers, a two (2) bit burst address counter
supporting four (4) double-word transfers. Writes are internally
self-timed and synchronous to the rising edge of clock.
CE1\
CE2
CE3\
BWE\
BWx\
GW\
ADV\
ADSC\
ADSP\
MODE
CONTROL
BLOCK
BURST CNTL.
Address
Registers
Row
Decode
I/O Gating and Control
Memory Array
x36
SBP
T Synchronous Pipeline
Burst
N Two (2) cycle load
N One (1) cycle
de-select
N One (1) cycle latency
on Mode change
Output Output
Register Driver
Input
Register
The AS5SP128K32 includes advanced control options including
Global Write, Byte Write as well as an Asynchronous Output
enable. Burst Cycle controls are handled by three (3) input pins,
ADV, ADSP\ and ADSC\. Burst operation can be initiated with
either the Address Status Processor (ADSP\) or Address Status
Cache controller (ADSC\) inputs. Subsequent
DQx, DQPxburst addresses are generated internally in the system’s burst
sequence control block and are controlled by Address Advance
(ADV) control input.
A0-Ax
Column
Decode
AS5SP128K32
Rev. 1.4 09/11
Micross Components reserves the right to change products or specications without notice.
1







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AS5SP128K32 Даташит, Описание, Даташиты
SSRAM
AS5SP128K32
PIN DESCRIPTION / ASSIGNMENT TABLE
Signal Name
Clock
Address
Address
Chip Enable
Chip Enable
Global Write Enable
Byte Enables
Byte Write Enable
Output Enable
Address Strobe Controller
Address Strobe from Processor
Address Advance
Power-Down
Data Input/Outputs
Burst Mode
Power Supply [Core]
Ground [Core]
Power Supply I/O
I/O Ground
No Connection(s)
Symbol
CLK
A0, A1
A
Type
Input
Input
Input(s)
CE1\, CE3\
CE2
GW\
BWa\, BWb\,
BWc\, BWd\
BWE\
OE\
ADSC\
Input
Input
Input
Input
Input
Input
Input
ADSP\
Input
ADV\
Input
ZZ Input
DQa, DQb, DQc Input/
DQd
Output
MODE
VDD
VSS
VDDQ
VSSQ
NC
Input
Supply
Supply
Supply
Supply
NA
Pin
89
37, 36
35, 34, 33, 32, 100,
99, 82, 81, 44, 45, 46,
47, 48, 49, 50
98, 92
97
88
93, 94, 95, 96
Description
This input registers the address, data, enables, Global and Byte
writes as well as the burst control functions
Low order, Synchronous Address Inputs and Burst counter
address inputs
Synchronous Address Inputs
Active Low True Chip Enables
Active High True Chip Enable
Active Low True Global Write enable. Write to all bits
Active Low True Byte Write enables. Write to byte segments
87
86
85
84
83
64
52, 53, 56, 57, 58, 59,
62, 63, 68, 69, 72, 73,
74, 75, 78, 79, 2, 3, 6,
7, 8, 9, 12, 13, 18, 19,
22, 23, 24, 25, 28, 29
31
91, 15, 41, 65
90, 17, 40, 67
4, 11, 20, 27, 54, 61,
70, 77
5, 10, 21, 26, 55, 60,
71, 76
1, 14, 16, 30, 38, 39,
51, 42,43, 66, 80
Active Low True Byte Write Function enable
Active Low True Asynchronous Output enable
Address Strobe from Controller. When asserted LOW, Address is
captured in the address registers and A0-A1 are loaded into the Burst
When ADSP\ and ADSC are both asserted, only ADSP is recognized
Synchronous Address Strobe from Processor. When asserted LOW,
Address is captured in the Address registers, A0-A1 is registered in
the burst counter. When both ADSP\ and ADSC\ or both asserted,
only ADSP\ is recognized. ADSP\ is ignored when CE1\ is HIGH
Advance input Address. When asserted HIGH, address in burst
counter is incremented.
Asynchronous, non-time critical Power-down Input control. Places
the chip into an ultra low power mode, with data preserved.
Bidirectional I/O Data lines. As inputs they reach the memory
array via an input register, the address stored in the register on the
rising edge of clock. As and output, the line delivers the valid data
stored in the array via an output register and output driver. The data
delieverd is from the previous clock period of the READ cycle.
Interleaved or Linear Burst mode control
Core Power Supply
Core Power Supply Ground
Isolated Input/Output Buffer Supply
Isolated Input/Output Buffer Ground
No connections to internal silicon
LOGIC BLOCK DIAGRAM
A0, A1, A
M ODE
ADV
CLK
A DSC
A DSP
BW D
BW C
BW B
BW A
BW E
GW
CE1
CE2
CE3
OE
ZZ
AS5SP128K32
Rev. 1.4 09/11
A DDR E SS
REGISTER
2 A [1:0]
Q1
BURST
COUNTER
CLR AND Q0
LOGIC
DQD
BYTE
W RITE REGISTER
DQC
BYTE
W RITE REGISTER
DQB
BYTE
W RITE REGISTER
DQA
BYTE
W RITE REGISTER
ENA BLE
REGISTER
PIPELINED
ENA BLE
SLEEP
CONTROL
DQD
BYTE
WRITE DRIVER
DQC
BYTE
WRITE DRIVER
DQB
BYTE
WRITE DRIVER
DQA
BYTE
WRITE DRIVER
M EM ORY
ARRAY
SENSE
AM PS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
E
DQs
INPUT
REGISTERS
Micross Components reserves the right to change products or specications without notice.
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AS5SP128K32 Даташит, Описание, Даташиты
SSRAM
AS5SP128K32
Functional Description
Micross Components AS5SP128K32 Synchronous SRAM is
manufactured to support today’s High Performance platforms
utilizing the Industries leading Processor elements including
those of Intel and Motorola. The AS5SP128K32 supports Syn-
chronous SRAM READ and WRITE operations as well as Syn-
chronous Burst READ/WRITE operations. All inputs with the
exception of OE\, MODE and ZZ are synchronous in nature
and sampled and registered on the rising edge of the devices
input clock (CLK). The type, start and the duration of Burst
Mode operations is controlled by MODE, ADSC\, ADSP\ and
ADV as well as the Chip Enable pins CE1\, CE2, and CE3\.
All synchronous accesses including the Burst accesses are
enabled via the use of the multiple enable pins and wait state
insertion is supported and controlled via the use of the Ad-
vance control (ADV).
The AS5SP128K32 supports both Interleaved as well as Lin-
ear Burst modes therefore making it an architectural t for ei-
ther the Intel or Motorola CISC processor elements available
on the Market today.
The AS5SP128K32 supports Byte WRITE operations and en-
ters this functional mode with the Byte Write Enable (BWE\)
and the Byte Write Select pin(s) (BWa\, BWb\, BWc\, BWd\).
Global Writes are supported via the Global Write Enable (GW\)
and Global Write Enable will override the Byte Write inputs and
will perform a Write to all Data I/Os.
The AS5SP128K32 provides ease of producing very dense-
arrays via the multiple Chip Enable input pins and Tri-state
outputs.
Single Cycle Access Operations
A Single READ operation is initiated when all of the following
conditions are satised at the time of Clock (CLK) HIGH: [1]
ADSP\ or ADSC\ is asserted LOW, [2] Chip Enables are all
asserted active, and [3] the WRITE signals (GW\, BWE\) are in
their FALSE state (HIGH). ADSP\ is ignored if CE1\ is HIGH.
The address presented to the Address inputs is stored within
the Address Registers and Address Counter/Advancement
Logic and then passed or presented to the array core. The
corresponding data of the addressed location is propagated to
the Output Registers and passed to the data bus on the next
rising clock via the Output Buffers. The time at which the data
is presented to the Data bus is as specied by either the Clock
to Data valid specication or the Output Enable to Data Valid
spec for the device speed grade chosen. The only exception
occurs when the device is recovering from a deselected to se-
lect state where its outputs are tristated in the rst machine
cycle and controlled by its Output Enable (OE\) on following
cycle. Consecutive single cycle READS are supported. Once
the READ operation has been completed and deselected by
use of the Chip Enable(s) and either ADSP\ or ADSC\, its out-
puts will tri-state immediately.
A Single ADSP\ controlled WRITE operation is initiated when
both of the following conditions are satised at the time of
Clock (CLK) HIGH: [1] ADSP\ is asserted LOW, and [2] Chip
Enable(s) are asserted ACTIVE. The address presented to the
address bus is registered and loaded on CLK HIGH, then pre-
sented to the core array. The WRITE controls Global Write,
and Byte Write Enable (GW\, BWE\) as well as the individual
Byte Writes (BWa\, BWb\, BWc\, and BWd\) and ADV\ are ig-
nored on the rst machine cycle. ADSP\ triggered WRITE ac-
cesses require two (2) machine cycles to complete. If Global
Write is asserted LOW on the second Clock (CLK) rise, the
data presented to the array via the Data bus will be written
into the array at the corresponding address location specied
by the Address bus. If GW\ is HIGH (inactive) then BWE\ and
one or more of the Byte Write controls (BWa\, BWb\, BWc\ and
BWd\) controls the write operation. All WRITES that are initi-
ated in this device are internally self timed.
A Single ADSC\ controlled WRITE operation is initiated when
the following conditions are satised: [1] ADSC\ is asserted
LOW, [2] ADSP\ is de-asserted (HIGH), [3] Chip Enable(s) are
asserted (TRUE or Active), and [4] the appropriate combina-
tion of the WRITE inputs (GW\, BWE\, BWx\) are asserted
(ACTIVE). Thus completing the WRITE to the desired Byte(s)
or the complete data-path. ADSC\ triggered WRITE accesses
require a single clock (CLK) machine cycle to complete. The
address presented to the input Address bus pins at time of
clock HIGH will be the location that the WRITE occurs. The
ADV pin is ignored during this cycle, and the data WRITTEN to
the array will either be a BYTE WRITE or a GLOBAL WRITE
depending on the use of the WRITE control functions GW\ and
BWE\ as well as the individual BYTE CONTOLS (BWx\).
Deep Power-Down Mode (SLEEP)
The AS5SP128K32 has a Deep Power-Down mode and is
controlled by the ZZ pin. The ZZ pin is an Asynchronous input
and asserting this pin places the SSRAM in a deep power-
down mode (SLEEP). While in this mode, Data integrity is
guaranteed. For the device to be placed successfully into this
operational mode the device must be deselected and the Chip
Enables, ADSP\ and ADSC\ remain inactive for the duration
of tZZREC after the ZZ input returns LOW. Use of this deep
power-down mode conserves power and is very useful in mul-
tiple memory page designs where the mode recovery time can
be hidden.
AS5SP128K32
Rev. 1.4 09/11
Micross Components reserves the right to change products or specications without notice.
3










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