PDF AS5SP128K32 Data sheet ( Hoja de datos )

Número de pieza	AS5SP128K32
Descripción	Synchronous SRAM
Fabricantes	Micross Components
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SSRAM AS5SP128K32 Plastic Encapsulated Microcircuit 4.0Mb, 128K x 32, Synchronous SRAM Pipeline Burst, Single Cycle Deselect FEATURES • Synchronous Operation in relation to the input Clock • 2 Stage Registers resulting in Pipeline operation • On chip address counter (base +3) for Burst operations • Self-Timed Write Cycles • On-Chip Address and Control Registers • Byte Write support • Global Write support • On-Chip low power mode [powerdown] via ZZ pin • Interleaved or Linear Burst support via Mode pin • Three Chip Enables for ease of depth expansion without Data Contention. • Two Cycle load, Single Cycle Deselect • Asynchronous Output Enable (OE\) • Three Pin Burst Control (ADSP\, ADSC\, ADV\) • 3.3V Core Power Supply • 3.3V/2.5V IO Power Supply • JEDEC Standard 100 pin TQFP Package • Available in Industrial, Enhanced, and Mil-Temperature Operating Ranges • TQFP in copper lead frame for superior thermal performance • RoHs compliant options available NC DQc DQc VDDQ VSSQ DQc DQc DQc DQc VSSQ VDDQ DQc DQc NC VDD NC VSS DQd DQd VDDQ VSSQ DQd DQd DQd DQd VSSQ VDDQ DQd DQd NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 SSRAM [SPB] 80 NC 79 DQb 78 DQb 77 VDDQ 76 VSSQ 75 DQb 74 DQb 73 DQb 72 DQb 71 VSSQ 70 VDDQ 69 DQb 68 DQb 67 VSS 66 NC 65 VDD 64 ZZ 63 DQa 62 DQa 61 VDDQ 60 VSSQ 59 DQa 58 DQa 57 DQa 56 DQa 55 VSSQ 54 VDDQ 53 DQa 52 DQa 51 NC FAST ACCESS TIMES Parameter CycleTime ClockAccessTime OutputEnableAccessTime Symbol 200Mhz 166Mhz 133Mhz 100Mhz Units tCYC 5.0 6.0 7.5 10.0 ns tCD 3.0 3.5 4.0 5.0 ns tOE 3.0 3.5 4.0 5.0 ns GENERAL DESCRIPTION The AS5SP128K32 is a 4.0Mb High Performance Synchronous BLOCK DIAGRAM OE\ ZZ CLK Pipeline Burst SRAM, available in multiple temperature screening levels, fabricated using High Performance CMOS technology and is organized as a 128K x 32. It integrates address and control registers, a two (2) bit burst address counter supporting four (4) double-word transfers. Writes are internally self-timed and synchronous to the rising edge of clock. CE1\ CE2 CE3\ BWE\ BWx\ GW\ ADV\ ADSC\ ADSP\ MODE CONTROL BLOCK BURST CNTL. Address Registers Row Decode I/O Gating and Control Memory Array x36 SBP T Synchronous Pipeline Burst N Two (2) cycle load N One (1) cycle de-select N One (1) cycle latency on Mode change Output Output Register Driver Input Register The AS5SP128K32 includes advanced control options including Global Write, Byte Write as well as an Asynchronous Output enable. Burst Cycle controls are handled by three (3) input pins, ADV, ADSP\ and ADSC\. Burst operation can be initiated with either the Address Status Processor (ADSP\) or Address Status Cache controller (ADSC\) inputs. Subsequent DQx, DQPxburst addresses are generated internally in the system’s burst sequence control block and are controlled by Address Advance (ADV) control input. A0-Ax Column Decode AS5SP128K32 Rev. 1.4 09/11 Micross Components reserves the right to change products or speciﬁcations without notice. 1 1 page SSRAM AS5SP128K32 DC ELECTRICAL CHARACTERISTICS (VDD=3.3v -5%/+10%, TA= Min. and Max temperatures of Screening level chosen) Symbol VDD VDDQ VoH VoL VIH VIL IIL IZZL IOL IDD ISB1 ISB2 ISB4 ISB3 Parameter Power Supply Voltage I/O Supply Voltage Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Input Leakage (except ZZ) Input Leakage, ZZ pin Output Leakage Operating Current Automatic CE. Power-down Current -TTL inputs Automatic CE. Power-down Current - CMOS Inputs Automatic CE. Power-down Current -TTL inputs Automatic CE. Power-down Current - CMOS Inputs Test Conditions VDD=Min., IOH=-4mA VDD=Min., IOH=-1mA VDD=Min., IOL=8mA VDD=Min., IOL=1mA VDD=Max., VIN=VSS to VDD 3.3v 2.5v 3.3v 2.5v 3.3v 2.5v 3.3v 2.5v Output Disabled, VOUT=VSSQ to VDDQ VDD=Max., f=Max., 5.0ns Cycle, 200 Mhz IOH=0mA 6.0ns Cycle, 166 Mhz 7.5ns Cycle, 133 Mhz 10 ns Cycle, 100 Mhz Max. VDD, Device De-Selected, VIN>/=VIH or VIN</=VIL 5.0ns Cycle, 200 Mhz f=fMAX=1/tCYC 6.0ns Cycle, 166 Mhz 7.5ns Cycle, 133 Mhz 10 ns Cycle, 100 Mhz Max. VDD, Device De-Selected, VIN</=0.3v or VIN>/=VDDQ-0.3v f=fMAX=1/tCYC Max. VDD, Device De-Selected, VIN>/=VIH or VIN </= VIL, f=0 Max. VDD, Device De-Selected, or VIN</=0.3v or VIN >/=VDDQ-0.3v, f-Max=1/tCYC 5.0ns Cycle, 200 Mhz 6.0ns Cycle, 166 Mhz 7.5ns Cycle, 133 Mhz 10 ns Cycle, 100 Mhz Min 3.135 2.375 2.4 2 2 1.7 -0.3 -0.3 -5 -30 -5 Max 3.630 VDD 0.4 0.4 VDD+0.3 VDD+0.3 0.8 0.7 5 30 5 265 240 225 205 Units V V V V V V V V V V uA uA uA mA mA mA mA 110 mA 100 mA 90 mA 80 mA 65 mA 70 mA Notes 1 1,5 1,4 1,4 1,4 1,4 1,2 1,2 1,2 1,2 3 3 95 mA 85 mA 75 mA 65 mA THERMAL RESISTANCE Parameter Description ȺJA ThermalResistance (JunctiontoAmbient) ȺJC ThermalResistance (JunctiontoCase) TestConditions Testconditionsfollowstandardtest methodsandproceduresfor measuringthermalimpedance,per EIA/JESD51 DQ DQC Package Package Unit 42 35.25 oC/W 9 7.96 oC/W Notes: [1] All Voltages referenced to VSS (Logic Ground) [2] Overshoot: VIH < +4.6V for t<tKC/2 for I<20mA Undershoot: VIL >-0.7V for t<tKC/2 for I<20mA Power-up: VIH <+3.6V and VDD<3.135V for t<200ms [3] MODE and ZZ pins have internal pull-up resistors, and input leakage +/> +10uA [4] The load used for VOH, VOL testing is shown in Figure-2 for 3.3v and 2.5V supplies. AC load current is higher than stated values, AC I/O curves can be made available upon request [5] VDDQ should never exceed VDD, VDD and VDDQ can be connected together [6] This parameter is sampled AS5SP128K32 Rev. 1.4 09/11 Micross Components reserves the right to change products or speciﬁcations without notice. 5 5 Page SSRAM AS5SP128K32 MECHANICAL DEFINITION 100-Pin TQFP (Package Designator DQ) 51-85050-*C AS5SP128K32 Rev. 1.4 09/11 11 Micross Components reserves the right to change products or speciﬁcations without notice. 11 Page

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