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AS5SP256K36 Datasheet Download - Micross Components

Номер произв AS5SP256K36
Описание Synchronous SRAM
Производители Micross Components
логотип Micross Components логотип 



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AS5SP256K36 Даташит, Описание, Даташиты
COTS PEM
SSRAM
AS5SP256K36
Plastic Encapsulated Microcircuit
9.0Mb, 256K x 36, Synchronous SRAM
Pipeline Burst, Single Cycle Deselect
FEATURES
Synchronous Operation in relation to the input Clock
2 Stage Registers resulting in Pipeline operation
On chip address counter (base +3) for Burst operations
Self-Timed Write Cycles
On-Chip Address and Control Registers
Byte Write support
Global Write support
On-Chip low power mode [powerdown] via ZZ pin
Interleaved or Linear Burst support via Mode pin
Three Chip Enables for ease of depth expansion without
Data Contention.
Two Cycle load, Single Cycle Deselect
Asynchronous Output Enable (OE\)
Three Pin Burst Control (ADSP\, ADSC\, ADV\)
DQPc
DQc
DQc
VDDQ
VSSQ
DQc
DQc
DQc
DQc
VSSQ
VDDQ
DQc
DQc
NC
VDD
NC
VSS
DQd
DQd
VDDQ
VSSQ
DQd
DQd
DQd
DQd
VSSQ
VDDQ
DQd
DQd
DQPd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SSRAM [SPB]
80 DQP
79 DQb
78 DQb
77 VDD
76 VSSQ
75 DQb
74 DQb
73 DQb
72 DQb
71 VSSQ
70 VDDQ
69 DQb
68 DQb
67 VSS
66 NC
65 VDD
64 ZZ
63 DQa
62 DQa
61 VDD
60 VSSQ
59 DQa
58 DQa
57 DQa
56 DQa
55 VSSQ
54 VDD
53 DQa
52 DQa
51 DQP
3.3V Core Power Supply
3.3V/2.5V IO Power Supply
JEDEC Standard 100 pin TQFP Package,
Available in Industrial, Enhanced, and Mil-Temperature FAST ACCESS TIMES
Operating Ranges
TQFP in copper lead frame* for superior thermal
performance
Parameter
Cycle Time
Clock Access Time
Output Enable Access Time
Symbol
tCYC
tCD
tOE
200Mhz
5.0
3.0
3.0
166Mhz
6.0
3.5
3.5
133Mhz
7.5
4.0
4.0
Units
ns
ns
ns
RoHs compliant options available
*Consult factory for copper lead frame products
GENERAL DESCRIPTION
The AS5SP256K36 is a 9.0Mb High Performance
Synchronous Pipeline Burst SRAM, available in multiple
temperature screening levels, fabricated using High
BLOCK DIAGRAM
OE\
ZZ
CLK
CE1\
Performance CMOS technology and is organized as a
256K x 36. It integrates address and control registers,
a two (2) bit burst address counter supporting four (4)
double-word transfers. Writes are internally self-timed
and synchronous to the rising edge of clock.
CE2
CE3\
BWE\
BWx\
GW\
ADV\
ADSC\
ADSP\
MODE
A0-Ax
CONTROL
BLOCK
BURST CNTL.
Address
Registers
Row
Decode
Column
Decode
I/O Gating and Control
Memory Array
x36
SBP
Synchronous Pipeline
Burst
Two (2) cycle load
One (1) cycle
de-select
One (1) cycle latency
on Mode change
Output Output
Register Driver
Input
Register
The AS5SP256K36 includes advanced control options
including Global Write, Byte Write as well as an
Asynchronous Output enable. Burst Cycle controls
are handled by three (3) input pins, ADV\, ADSP\ and
ADSC\. Burst operation can be initiated with either the
DQx, DQP Address Strobe Processor (ADSP\) or Address Strobe
controller (ADSC\) inputs. Subsequent burst addresses
are generated internally in the system’s burst sequence
control block and are controlled by Address Advance
(ADV\) control input.
AS5SP256K36
Rev. 2.1 09/11
Micross Components reserves the right to change products or specications without notice.
1







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AS5SP256K36 Даташит, Описание, Даташиты
COTS PEM
SSRAM
AS5SP256K36
PIN DESCRIPTION / ASSIGNMENT TABLE
Signal Name
Clock
Address
Address
Chip Enable
Chip Enable
Global Write Enable
Byte Enables
Byte Write Enable
Output Enable
Address Strobe Controller
Address Strobe from Processor
Address Advance
Power-Down
Data Parity Input/Outputs
Data Input/Outputs
Burst Mode
Power Supply [Core]
Ground [Core]
Power Supply I/O
I/O Ground
No Connection(s)
Symbol
CLK
A0, A1
A
Type
Input
Input
Input(s)
CE1\, CE3\
CE2
GW\
BWa\, BWb\,
BWc\, BWd\
BWE\
OE\
ADSC\
Input
Input
Input
Input
Input
Input
Input
ADSP\
Input
ADV\
ZZ
DQPa, DQPb
DQPc, DQPd
Input
Input
Input/
Output
DQa, DQb, DQc Input/
DQd
Output
MODE
VDD
VSS
VDDQ
VSSQ
NC
Input
Supply
Supply
Supply
Supply
NA
Pin Description
89 This input captures all synchronous inputs to the device as well as
synchronizes the burst control functions.
37, 36
Low order, Synchronous Address Inputs and Burst counter
address inputs
35, 34, 33, 32, 31, 100, Synchronous Address Inputs
99, 82, 81, 44, 45, 46,
47, 48, 49, 50, 43
98, 92
Active Low True Chip Enables
97 Active High True Chip Enable
88 Active Low True Global Write enable. Write to all bits
93, 94, 95, 96
Active Low True Byte Write enables. Write to byte segments
87 Active Low True Byte Write Function enable
86 Active Low True Asynchronous Output enable
85 Address Strobe from Controller. When asserted LOW, Address is
captured in the address registers and A0-A1 are loaded into the Bur
When ADSP\ and ADSC are both asserted, only ADSP is recognized
84 Address Strobe from Processor. When asserted LOW,
Address is captured in the Address registers, A0-A1 is registered in
the burst counter. When both ADSP\ and ADSC\ or both asserted,
only ADSP\ is recognized. ADSP\ is ignored when CE1\ is HIGH
83 Advance input Address. When asserted LOW, address in burst
counter is incremented.
64 Asynchronous, non-time critical Power-down Input control. Places
the chip into an ultra low power mode, with data preserved.
51, 80, 1, 30
Bidirectional I/O Parity lines. As inputs they reach the memory
array via data register, that is triggered on the
rising edge of clock. As an output, the line delivers the valid data
stored in the array via an output register and output driver. The data
delievered is from the previous clock period of the READ cycle.
52, 53, 56, 57, 58, 59, Bidirectional I/O Parity lines. As inputs they reach the memo
62, 63, 68, 69, 72, 73, array via data register, that is triggered on the
74, 75, 78, 79, 2, 3, 6, rising edge of clock. As an output, the line delivers the valid data
7, 8, 9, 12, 13, 18, 19, stored in the array via an output register and output driver. The data
22, 23, 24, 25, 28, 29 delievered is from the previous clock period of the READ cycle.
31 Interleaved or Linear Burst mode control
91, 15, 41, 65
Core Power Supply
90, 17, 40, 67
Core Power Supply Ground
4, 11, 20, 27, 54, 61, Isolated Input/Output Buffer Supply
70, 77
5, 10, 21, 26, 55, 60, Isolated Input/Output Buffer Ground
71, 76
14, 16, 38, 39, 65 No connections to internal silicon
AS5SP256K36
Rev. 2.1 09/11
Micross Components reserves the right to change products or specications without notice.
2







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AS5SP256K36 Даташит, Описание, Даташиты
LOGIC BLOCK DIAGRAM
A 0, A1, A
MODE
ADV
CLK
ADSC
ADSP
BW D
BW C
BW B
BW A
BWE
GW
CE 1
CE 2
CE 3
OE
ADDRESS
REGISTER
2 A [1:0]
Q1
BURST
COUNTER
CLR AND Q0
LOGIC
DQ D ,DQP D
BYTE
WRITE REGISTER
DQ C ,DQP C
BYTE
WRITE REGISTER
DQ B ,DQP B
BYTE
WRITE REGISTER
DQ A ,DQP A
BYTE
WRITE REGISTER
ENABLE
REGISTER
PIPELINED
ENABLE
ZZ SLEEP
CONTROL
DQ D ,DQPD
BYTE
WRITE DRIVER
DQ C ,DQP C
BYTE
WRITE DRIVER
DQ B ,DQP B
BYTE
WRITE DRIVER
DQ A ,DQP A
BYTE
WRITE DRIVER
COTS PEM
SSRAM
AS5SP256K36
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
E
DQs
DQP A
DQP B
DQP C
DQP D
INPUT
REGISTERS
AS5SP256K36
Rev. 2.1 09/11
Micross Components reserves the right to change products or specications without notice.
3










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