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AS5SS512K36 Datasheet Download - Micross Components

Номер произв AS5SS512K36
Описание 512K x 36 SSRAM
Производители Micross Components
логотип Micross Components логотип 



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AS5SS512K36 Даташит, Описание, Даташиты
SSRAM
AS5SS512K36
512K x 36 SSRAM
Flow-Through SRAM
No Bus Latency
PIN ASSIGNMENT
(Top View)
100-Pin TQFP (DQ)
AVAILABLE AS MILITARY
SPECIFICATIONS
•MIL-STD-883
FEATURES
• Pin compatible and functionally equivalent to ZBT devices.
• Supports 133MHz bus operations with zero wait states
-Data is transferred on every clock
• Internally self-timed output buffer control to eliminate the need
to use asynchronous OE\
• Registered inputs for Flow-Through operation
• Byte Write capability
• Common I/O architecture
• Fast clock-to-output times
-6.5ns (for 133 MHz device)*
-8.5ns (for 100 MHz device)
• Single 3.3V -5% and +1-% power supply V
DD
• Separate VDD for 3.3V or 2.5V I/O
• Clock Enable (CEN\) pin to suspend operation
• Synchronous self-timed writes
• Available in 100-pin TSOP package.**
• Burst Capability - linear or interleaved burst order
• No bus latency architecture eliminated dead cycles between write
and read cyccles
OPTIONS
• Timing
6.5ns access
8.5ns access
MARKING
-6.5*
-8.5
• Operating Temperature Ranges
Military (-55oC to +125oC) XT
Industrial (-40oC to +85oC) IT
• Package(s)**
100-pin TQFP
DQ
NOTES:
* 6.5ns speed available with IT option only.
**Contact factory for BGA package interests.
GENERAL DESCRIPTION
The AS5SS512K36D is is a 3.3V, 512K x 36 Synchronous
ow through Burst SRAM designed specically to support
unlimited true back-to-back Read/Write operations with no
wait state insertion. The AS5SS512K36D is equipped with the
advanced No Bus Latency logic required to enable consecutive
Read/Write operations with data being transferred on every
clock cycle. This feature dramatically improves the throughput
BYTE C
BYTE D
DQPC
DQC
DQC
VDDQ
VSS
DQC
DQC
DQC
DQC
VSS
VDDQ
DQC
DQC
NC
VDD
NC
VSS
DQD
DQD
VDDQ
VSS
DQD
DQD
DQD
DQD
VSS
VDDQ
DQD
DQD
DQPD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1371D
80 DQPB
79 DQB
78 DQB
77 VDDQ
76 VSS
75
74
DQB
DQB
BYTE B
73 DQB
72 DQB
71 VSS
70 VDDQ
69 DQB
68 DQB
67 VSS
66 NC
65 VDD
64 ZZ
63 DQA
62 DQA
61 VDDQ
60 VSS
59 DQA
58 DQA
57
DQA
BYTE A
56 DQA
55 VSS
54 VDDQ
53 DQA
52 DQA
51 DQPA
All synchronous inputs pass through input registers controlled by the
rising edge of the clock. The clock input is qualied by the Clock
Enable (CEN) signal, which when deasserted suspends operation and
extends the previous clock cycle. Maximum access delay from the
clock rise is 6.5 ns (133-MHz device). Write operations are controlled
by the two or four Byte Write Select (BWX) and a Write Enable (WE)
input. All writes are conducted with on-chip synchronous self-timed
write circuitry. Three synchronous Chip Enables (CE1, CE2, CE3)
and an asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. To avoid bus contention, the
output drivers are synchronously tri-stated during the data portion of
a write sequence.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock input is qualied by the Clock
Enable (CEN\) signal, which when deasserted suspends operation and
extends the previous clock cycle.
Write operations are controlled by the Byte Write Selects (BWS\
a,b,c,d) and a Write Enable (WE\) input. All writes are conducted
with on-chip synchronous self-timed write circuitry.
Synchronous Chip Enable (CE1\, CE2, CE3\) and an
asynchronous Output Enable (OE\) provide for easy bank selection
and output three-state control. In order to avoid bus contention, the
output drivers are synchronously three-stated during the data portion
of a write sequence.
For more products and information
of data through the SRAM, especially in systems that require
frequent Write-Read transitions.
please visit our web site at
www.micross.com
AS5SS512K36
Rev. 0.6 01/10
Micross Components reserves the right to change products or specications without notice.
1







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AS5SS512K36 Даташит, Описание, Даташиты
SSRAM
AS5SS512K36
FUNCTIONAL BLOCK DIAGRAM
A0, A1, A
MODE
CLK C
CEN
CE
ADV/LD
BW A
BW B
BW C
BW D
WE
OE
CE1
CE2
CE3
ZZ
ADDRESS
REGISTER
A1
A0
D1
D0
ADV/LD
C
WRITE ADDRESS
REGISTER
BURST
LOGIC
Q1
Q0
A1'
A0'
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
READ LOGIC
SLEEP
CONTROL
INPUT E
REGISTER
O
U
T
DP
AU
TT
A
B
SU
TF
EF
EE
RR
IS
NE
G
DQs
DQP A
DQP B
DQP C
DQP D
SELECTION GUIDE
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
133 MHz
6.5
210
70
100 MHz
8.5
175
70
UNITS
ns
mA
mA
AS5SS512K36
Rev. 0.6 01/10
Micross Components reserves the right to change products or specications without notice.
2







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AS5SS512K36 Даташит, Описание, Даташиты
SSRAM
AS5SS512K36
PIN DEFINITIONS
PIN
AO
A1
A
BWa\
BWb\
BWc\
BWd\
WE\
ADV/LD\
CLK
CE1\
CE2\
CE3\
OE\
CEN\
ZZ
DQa
DQb
DQc
DQd
DPa
DPb
DPc
DPd
MODE
VDD
VDDQ
VSS
NC
I/O TYPE
Input-
Synchronous
DESCRIPTION
Address Inputs used to select one of the address locations. Sampled at the rising edge of
the CLK. A[1:0] are fed to the two-bit burst counter.
Input-
Byte Write Inputs, Active LOW. Qualified with WE to conduct writes to the SRAM.
Synchronous Sampled on the rising edge of CLK.
Input-
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN\ is active
Synchronous LOW. This signal must be asserted LOW to initiate a write sequence.
Input-
Synchronous
Advanced/Lowed Input used to advance the on-chip address counter or load a new
address. When HIGH (and CEN\ is asserted LOW) the internal burst counter is
advanced. When LOW, a new address can be loaded into the device for an access. After
being deselected, ADV/LD\ should be driven LOW in order to load a new address.
Input-Clock
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with
CEN\. CLK is only recognized if CEN\ is active LOW.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE2 and CE3\ to select/deselect the device.
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE1\ and CE3\ to select/deselect the device.
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE1\ and CE2 to select/deselect the device.
Input-
Asynchronous
Output Enable, active LOW. Combined with the synchronous logic block inside the device
to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as
outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins.
OE\ is masked during the data portion of a write sequence, during the first clock when
emerging from a deselected state and when the device has been deselected.
Input-
Synchronous
Input-
Synchronous
Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by
the SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN\
does not deselect the device, CEN\ can be used to extend the previous cycle when
required.
ZZ “Sleep” Input. This active HIGH input places the device in a non-time critical “sleep”
condition with data integrity preserved. For normal operation, this pin has to be LOW or
left floating. ZZ pin has an internal pull down.
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by A[17:0] during the previous clock rise of the read cycle. The
I/O- Synchronous direction of the pins is controlled by OE\ and the internal control logic. When OE\ is
asserted LOW, the pins can behave as outputs. When HIGH, DQa - DQd are placed in a
three-state condition. The outputs are automatically three-stated during the data portion
of the write sequence, during the first clock when emerging from a deselected state, and
when the device is deselected, regardless of the state of OE\.
I/O- Synchronous Bidirectional Data Parity I/O lines. Functionally, these signals are identical to DQs.
Input Strap Pin
Power Supply
Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved
burst order. Pulled LOW selects the linear burst order. MODE should not change states
during operation. When left floating MODE will default HIGH, to an interleaved burst
order.
Power supply inputs to the core of the device.
I/O Power Supply Power supply for the I/O circuitry.
Ground
---
Ground for the device. Should be connected to the ground of the system.
No connects. Pins are not internally connected.
AS5SS512K36
Rev. 0.6 01/10
Micross Components reserves the right to change products or specications without notice.
3










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