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H5MS2562JFR PDF даташит

Спецификация H5MS2562JFR изготовлена ​​​​«Hynix Semiconductor» и имеет функцию, называемую «Mobile DDR SDRAM 256Mbit (16M x 16bit)».

Детали детали

Номер произв H5MS2562JFR
Описание Mobile DDR SDRAM 256Mbit (16M x 16bit)
Производители Hynix Semiconductor
логотип Hynix Semiconductor логотип 

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H5MS2562JFR Даташит, Описание, Даташиты
256Mbit MOBILE DDR SDRAM based on 4M x 4Bank x16 I/O
Specification of
256Mb (16Mx16bit) Mobile DDR SDRAM
Memory Cell Array
- Organized as 4banks of 4,194,304 x16
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev 1.2 / July. 2009
1









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H5MS2562JFR Даташит, Описание, Даташиты
256Mbit MOBILE DDR SDRAM based on 4M x 4Bank x16 I/O
Document Title
256Mbit (4Bank x 4M x 16bits) MOBILE DDR SDRAM
Revision History
Revision No.
History
0.1 - Initial Draft
0.2 - IDD Specification updated
1.0 - The final version
1.1 - Insert DDR370 DC/AC Characteristics
1.2 - Omit a typo in package information
Draft Date
May 2008
May 2008
Nov. 2008
Apr. 2009
July. 2009
Remark
Preliminary
Preliminary
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev 1.2 / July. 2009
2









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H5MS2562JFR Даташит, Описание, Даташиты
Mobile DDR SDRAM 256Mbit (16M x 16bit)
H5MS2562JFR Series
FEATURES SUMMARY
Mobile DDR SDRAM
- Double data rate architecture: two data transfer per
clock cycle
Mobile DDR SDRAM INTERFACE
- x16 bus width
- Multiplexed Address (Row address and Column ad-
dress)
SUPPLY VOLTAGE
- 1.8V device: VDD and VDDQ = 1.7V to 1.95V
MEMORY CELL ARRAY
- 256Mbit (x16 device) = 4M x 4Bank x 16 I/O
DATA STROBE
- x16 device: LDQS and UDQS
- Bidirectional, data strobe (DQS) is transmitted and re-
ceived with data, to be used in capturing data at the
receiver
- Data and data mask referenced to both edges of DQS
LOW POWER FEATURES
- PASR (Partial Array Self Refresh)
- AUTO TCSR (Temperature Compensated Self Refresh)
- DS (Drive Strength)
- DPD (Deep Power Down): DPD is an optional feature,
so please contact Hynix office for the DPD feature
INPUT CLOCK
- Differential clock inputs (CK, CK)
Data MASK
- LDM and UDM: Input mask signals for write data
- DM masks write data-in at the both rising and
falling edges of the data strobe
MODE RERISTER SET, EXTENDED MODE REGIS-
TER SET and STATUS REGISTER READ
- Keep to the JEDEC Standard regulation
(Low Power DDR SDRAM)
CAS LATENCY
- Programmable CAS latency 2 or 3 supported
BURST LENGTH
- Programmable burst length 2 / 4 / 8 with both sequen-
tial and interleave mode
AUTO PRECHARGE
- Option for each burst access
AUTO REFRESH AND SELF REFRESH MODE
CLOCK STOP MODE
- Clock stop mode is a feature supported by Mobile DDR
SDRAM.
- Keep to the JEDEC Standard regulation
INITIALIZING THE MOBILE DDR SDRAM
- Occurring at device power up or interruption of device
power
PACKAGE
- H5MS2562JFR: 60 Ball FBGA, Lead & Halogen free
This product is in compliance with the directive
pertaining of RoHS.
Rev 1.2 / July. 2009
3










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