PDF SEP04G72G1AH2MT-30R Data sheet ( Hoja de datos )

Número de pieza	SEP04G72G1AH2MT-30R
Descripción	SDRAM registered DIMM
Fabricantes	Swissbit
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No Preview Available ! Data Sheet Rev.1.2 14.02.2014 4GB DDR2 – SDRAM registered DIMM 240 Pin RDIMM SEP04G72G1AH2MT-xxR 4GByte in FBGA Technology RoHS compliant Options:  Data Rate / Latency DDR2 667 MT/s CL5 DDR2 800 MT/s CL6 Marking -30 -25  Module Density 4GByte with 36 dies and 2 ranks  Standard Grade (TC) (TA) 0°C to 85°C 0°C to 70°C Environmental Requirements:  Operating temperature (TC) Standard Grade  Operating Humidity 0°C to 85°C 10% to 90% relative humidity, noncondensing  Operating Pressure 105 to 69 kPa (up to 10000 ft.)  Storage Temperature -55°C to 100°C  Storage Humidity 5% to 95% relative humidity, noncondensing  Storage Pressure 1682 PSI (up to 5000 ft.) at 50°C Features:  240-pin 72-bit Dual-In-Line Double Data Rate Synchronous DRAM Module for server applications  Module organization: dual rank 512M x 64  VDD = 1.8V ±0.1V, VDDQ 1.8V ±0.1V  1.8V I/O ( SSTL_18 compatible)  Auto Refresh (CBR) and Self Refresh 8k Refresh every 64ms  Serial Presence Detect with EEPROM  Gold-contact pad  This module is fully pin and functional compatible to the JEDEC PC2-6400 spec. and JEDEC- Standard MO-237. (see www.jedec.org)  The pcb and all components are manufactured according to the RoHS compliance specification [EU Directive 2002/95/EC Restriction of Hazardous Substances (RoHS)]  DDR2 - SDRAM component MICRON MT47H256M4CF-25 DIE-Revision H  256Mx4 DDR2 SDRAM in FBGA-60 package  Four bit prefetch architecture  DLL to align DQ and DQS transitions with CK  Eight internal device banks for concurrent operation  Programmable CAS latency (CL)  Posted CAS additive latency (AL)  WRITE latency = READ latency – 1 tCK  Programmable burst length: 4 or 8  Adjustable data-output drive strength  On-die termination (ODT) Swissbit AG Industriestrasse 4 CH-9552 Bronschhofen mechanical dimensions Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com eMail: [email protected] Page 1 of 16 1 page Data Sheet Rev.1.2 14.02.2014 FUNCTIONAL BLOCK DIAGRAMM 4096MB DDR2 ECC Registered DIMM, 2 RANKS AND 36 COMPONENTS Swissbit AG Industriestrasse 4 CH-9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com eMail: [email protected] Page 5 of 16 5 Page Data Sheet Rev.1.2 14.02.2014 DDR2 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Continued) (0°C ≤ TCASE ≤ + 85°C ; VDDQ = +1.8V ± 0.1V, VDD = +1.8V ± 0.1V) AC CHARACTERISTICS Parameter ODT power-down exit latency ODT enable from MRS command Exit active power-down to READ command, MR [bit 12 = 0] Exit active power-down to READ command, MR [bit 12 = 1] Exit precharge power-down to any non-READ command CKE minimum high/low time Symbol tAXPD TMOD tXARD tXARDS tXP tCKE 6400-CL6 MIN MAX 8- 12 - 2- 8 – AL - 2- 3- 5300-CL5 MIN MAX 8- 12 - 2- 7 – AL - 2- 3- Unit tCK ns tCK tCK tCK tCK Register Specifications Parameter DC high-level input voltage DC low-level input voltage AC high-level input voltage AC low-level input voltage Output high voltage Output low voltage Input current Static standby Static operating Dynamic operating (clock tree) Dynamic operating (per each input) Input capacitance (per device, per pin) Input capacitance (per device, per pin) Symbol VIH(DC) VIL(DC) VIH(AC) VIL(AC) VOH VOL II IDD Pins Address, control, command Address, control, command Address, control, command Address, control, command Parity output Parity output All pins All pins IDD All pins IDDD n/a IDDD n/a CI Data CI RESET# Conditions SSTL_18 Min VREF(DC) + 125 SSTL_18 0 SSTL_18 VREF(DC) + 250 SSTL_18 0 LVCMOS LVCMOS VI = VDDQ or VSSQ RESET# = VSSQ (IO = 0) RESET# = VSSQ; VI = VIH(AC) or VIL(DC) IO = 0 RESET# = VDD, VI = VIH(AC) or VIL(AC), IO = 0; CK and CK# switching 50% duty cycle RESET# = VDD, VI = VIH(AC) or VIL(AC), IO = 0; CK and CK# switching 50% duty cycle; One data input switching at tCK/2, 50% duty cycle VI = VREF ±250mV; VDDQ = 1.8V VI = VDDQ or VSSQ 1.2 - -5 - - - - 2.5 - Max Units VDDQ + 250 mV VREF(DC) - 125 mV VDD mV VREF(DC) - 250 mV -V 0.5 V +5 µA 100 µA 40 mA Varies by manufacturer µA Varies by manufacturer µA 3.5 Varies by manufacturer pF pF Notes: 1. Timing and switching specifications for the register listed above are critical for proper operation of the DDR2 SDRAM registered DIMMs. These are meant to be a subset of the parameters for the specific device used on the module. Detailed information for this register is available in JEDEC standard JESD82. Swissbit AG Industriestrasse 4 CH-9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com eMail: [email protected] Page 11 of 16 11 Page

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