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PDF NT5TU64M16GG-BE Data sheet ( Hoja de datos )
| Número de pieza | NT5TU64M16GG-BE | |
| Descripción | 1Gb DDR2 SDRAM | |
| Fabricantes | Nanya | |
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NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Feature
CAS Latency Frequency
Speed Bins
-3C/3CI
(DDR2-667-CL5)
-AC/ACI/ACL
(DDR2-800-CL5)
-BE
(DDR2-1066-CL7)
Parameter
Min. Max. Min. Max.
Min.
Max.
Clock Frequency 125 333 125 400 125 533
tRCD
15 - 12.5 - 12.5 -
tRP 15 - 12.5 - 12.5 -
tRC 60 - 57.5 - 57.5 -
tRAS
40 70K 40 70K 40 70K
tCK(Avg.)@CL3 5 8 5 8 5 8
tCK(Avg.)@CL4 3.75 8 3.75 8
3.75
8
tCK(Avg.)@CL5 3 8 2.5 8 2.5 8
tCK(Avg.)@CL6
-
- 2.5 8 2.5 8
tCK(Avg.)@CL7
-
-
-
-
1.875
8
*The timing specification of high speed bin is backward compatible with low speed bin
-BD
(DDR2-1066-CL6)
Min.
Max.
125 533
11.25
-
11.25
-
56.25
-
40 70K
58
3.75 8
2.5 8
1.875
8
1.875
8
Units
tCK(Avg.)
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
VDD=VDDQ=1.8V ± 0.1V Voltage
Support Industrial grade temperature
JEDEC standard 1.8V I/O (SSTL_18 compatible)
(–40°C≦TC≦ 95°C; –40°C≦TA≦ +85°C)
8 internal memory banks
Programmable CAS Latency:
Support automotive grade 3 temperature
(–40°C≦TC≦ 95°C; –40°C≦TA≦ +85°C)
3, 4, 5 (-3C/3CI, -AC/ACI/ACL, -BE, -BD);
1KB page size for x8
6 (-AC/ACI/ACL, -BE, -BD);
2KB page size for x16
7 (-BE, -BD)
Strong and Weak Strength Data-Output Driver
Programmable Additive Latency: 0, 1, 2, 3, 4 5
Auto-Refresh and Self-Refresh
Write Latency = Read Latency -1
Programmable Burst Length:
Power Saving Power-Down modes
7.8 µs max. Average Periodic Refresh Interval
4 and 8 Programmable Sequential / Interleave Burst
RoHS Compliance and Halogen Free
OCD (Off-Chip Driver Impedance Adjustment)
AEC-Q100 for NT5TU128M8GE – ACI
ODT (On-Die Termination)
PPAP submission for NT5TU128M8GE – ACI
4n-bit prefetch architecture
Data-Strobes: Bidirectional, Differential
Packages: 60-Ball BGA for x8 components
84-Ball BGA for x16 components
REV 2.0
02/2013
1
© NANYA TECHNOLOGY CORP. All rights reserved
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
1 page  
NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Input / Output Functional Description
Symbol
Type
Function
Clock: CK and are differential clock inputs. All address and control input signals are sampled
CK,
Input
on the crossing of the positive edge of CK and negative edge of . Output (read) data is
referenced to the crossings of CK and (both directions of crossing).
CKE
, ,
Input
Input
Input
Clock Enable: CKE high activates, and CKE low deactivates, internal clock signals and device
input buffers and output drivers. Taking CKE low provides Precharge Power-Down and
Self-Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is
synchronous for power down entry and exit and for Self-Refresh entry. CKE is asynchronous for
Self-Refresh exit. After VREF has become stable during the power on and initialization sequence, it
must be maintained for proper operation of the CKE receiver. For proper self-refresh entry and
exit, VREF must maintain to this input. CKE must be maintained high throughout read and write
accesses. Input buffers, excluding CK, , ODT and CKE are disabled during Power Down. Input
buffers, excluding CKE, are disabled during Self-Refresh.
Chip Select: All commands are masked when is registered high. provides for external rank
selection on systems with multiple memory ranks. is considered part of the command code.
Command Inputs: , and (along with ) define the command being entered.
DM, LDM, UDM
BA0 - BA2
Input
Input
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is
sampled high coincident with that input data during a Write access. DM is sampled on both edges
of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. For
x8 device, the function of DM or RDQS / is enabled by EMRS command.
Bank Address Inputs: BA0, BA1, and BA2 define to which bank an Active, Read, Write or
Precharge command is being applied. Bank address also determines if the mode register or
extended mode register is to be accessed during a MRS or EMRS cycle.
A0 – A13
DQ
Address Inputs: Provides the row address for Activate commands and the column address and
Auto Precharge or Read/Write commands to select one location out of the memory array in the
Input
respective bank. A10 is sampled during a Precharge command to determine whether the
precharge applies to one bank (A10=low) or all banks (A10=high). If only one bank is to be
precharged, the bank is selected by BA0-BA2. The address inputs also provide the op-code during
Mode Register Set commands.A13 Row address use on x8 components only.
Input/output Data Inputs/Output: Bi-directional data bus.
DQS, ()
LDQS, (),
UDQS,()
Data Strobe: output with read data, input with write data. Edge aligned with read data, centered
with write data. For the x16, LDQS corresponds to the data on DQ0 - DQ7; UDQS corresponds to
Input/output
the data on DQ8-DQ15. The data strobes DQS, LDQS, UDQS, and RDQS may be used in single
ended mode or paired with the optional complementary signals , , and to provide
differential pair signaling to the system during both reads and writes. An EMRS(1) control bit
enables or disables the complementary data strobe signals.
REV 2.0
02/2013
5
© NANYA TECHNOLOGY CORP. All rights reserved
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
5 Page 
NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
- The VDDQ voltage ramp time from when VDD min is achieved on VDD to when VDDQ min is achieved on VDDQ must
be no greater than 500ms. (Note: While VDD is ramping, current may be supplied from VDD through the DRAM to
VDDQ.)
- Vref must track VDDQ/2; Vref must be within ±300mV with respect to VDDQ/2 during supply ramp time.
- VDDQ ≧ VREF must be met at all time.
- Apply VTT.
2. Start clock (CK, ) and maintain stable condition.
3. For the minimum of 200us after stable power (VDD, VDDL, VDDQ, VREF, and VTT are between their minimum and
maximum values as stated in Re-commanded DC operating conditions table, and stable clock, then apply NOP or
Deselect & take CKE HIGH.
4. Waiting minimum of 400ns then issue pre-charge all command. NOP or Deselect applied during 400ns period.
5. Issue an EMRS command to EMR (2). (Provide LOW to BA0 and BA2, and HIGH to BA1).
6. Issue an EMRS command to EMR (3). (Provide LOW to BA2 and HIGH to BA0 and BA1).
7. Issue EMRS to enable DLL. (Provide Low to A0, HIGH to BA0 and LOW to BA1-BA2 and A13-A15. And
A9=A8=A7=LOW must be used when issuing this command.)
8. Issue a Mode Register Set command for DLL reset. (Provide HIGH to A8 and LOW to BA0-BA2, and A13-A15.)
9. Issue a precharge all command.
10. Issue 2 more auto-refresh commands.
11. Issue a MRS command with LOW to A8 to initialize device operation (i.e. to program operating parameters without
resetting the DLL.)
12. At least 200 clocks after step 7, execute OCD Calibration (Off Chip Driver impedance adjustment). If OCD calibration
is not used, EMRs to EMR (1) to set OCD Calibration Default (A9=A8=A7=HIGH) followed by EMRS to EMR (1) to exit
OCD Calibration Mode (A9=A8=A7=LOW) must be issued with other operating parameters of EMR (1).
13. The DDR2 DRAM is now ready for normal operation.
* To guarantee ODT off, VREF must be valid and a low level must be applied to the ODT pin.
Example
CK, CK
CKE
ODT "low"
400 ns
NOP
PRE
ALL
Command
CMD
tRP
tMRD
tMRD
EMRS
Extended Mode
Register Set
with DLL enable
MRS
Mode Register Set
with DLL reset
Follow OCD
tRP
tRFC
tRFC
tMRD
flowchart
PRE
ALL
1st Auto
refresh
2nd Auto
refresh
MRS
EMRS
EMRS
min. 200 cycles to
lock the DLL
Follow OCD
flowchart
REV 2.0
02/2013
11
© NANYA TECHNOLOGY CORP. All rights reserved
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet NT5TU64M16GG-BE.PDF ] | |
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