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SEP02G72E2BF2SA-37R PDF даташит

Спецификация SEP02G72E2BF2SA-37R изготовлена ​​​​«Swissbit» и имеет функцию, называемую «SDRAM registered DIMM».

Детали детали

Номер произв SEP02G72E2BF2SA-37R
Описание SDRAM registered DIMM
Производители Swissbit
логотип Swissbit логотип 

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SEP02G72E2BF2SA-37R Даташит, Описание, Даташиты
Data Sheet
Rev.1.0 23.11.2010
2GB DDR2 SDRAM registered DIMM
240 Pin RDIMM
SEP02G72E2BF2SA-30R
2GB PC2-5300 in FBGA Technology
RoHS compliant
Options:
Data Rate / Latency
DDR2 533 MTs / CL4
DDR2 667 MT/s / CL5
Marking
-37
-30
Module Density
2048MB with 18 dies and 2 ranks
Standard Grade (TA)
(TC)
0°C to 70°C
0°C to 85°C
Environmental Requirements:
Operating temperature (TAMBIENT)
Standard Grade
Operating Humidity
0°C to 70°C
10% to 90% relative humidity, noncondensing
Operating Pressure
105 to 69 kPa (up to 10000 ft.)
Storage Temperature
-55°C to 100°C
Storage Humidity
5% to 95% relative humidity, noncondensing
Storage Pressure
1682 PSI (up to 5000 ft.) at 50°C
Features:
240-pin 72-bit DDR2 registered Dual-In-Line Double Data
Rate Synchronous DRAM Module for server applications
Module organization: dual rank 256M x 72
VDD = 1.8V ±0.1V, VDDQ 1.8V ±0.1V
1.8V I/O ( SSTL_18 compatible)
Serial Presence Detect with EEPROM
Supports ECC error detection and correction
JEDEC compatible DDR2 PLL/Register component with
parity bit support for address and control bus
Gold-contact pad
This module family is fully pin and functional compatible
to JEDEC. (see www.jedec.org)
The pcb and all components are manufactured according
to the RoHS compliance specification
[EU Directive 2002/95/EC Restriction of Hazardous
Substances (RoHS)]
DDR2 SDRAM component Samsung K4T1G084QF
128Mx8 DDR2 SDRAM in FBGA-60 package
Four bit prefetch architecture
Programmable CAS latency (CL)
Posted CAS additive latency (AL)
WRITE latency = READ latency 1 tCK
Programmable burst length: 4 or 8
Adjustable data-output drive strength
On-die termination (ODT)
DLL to align DQ and DQS transitions with CK
Figure: mechanical dimensions1
Swissbit AG
Industriestrasse 4
CH 9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
1if no tolerances specified ± 0.15mm
www.swissbit.com
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SEP02G72E2BF2SA-37R Даташит, Описание, Даташиты
Data Sheet
Rev.1.0 23.11.2010
This Swissbit module is an industry standard 240-pin 8-byte DDR2 registered SDRAM Dual-In-line Memory
Module (RDIMM) which is organized as x72 high speed CMOS memory arrays. All control and address signals
are re-driven on the DIMM using register devices and a PLL for the clock distribution. This reduces capacitive
loading to the system bus, but adds one cycle to the SDRAM timing. De-coupling capacitors, stub resistors,
calibration resistors and termination resistors are mounted on the PCB board. The module uses double data rate
architecture to achieve high-speed operation. DDR2 SDRAM modules operate from a differential clock (CK and
CK#). READ and WRITE accesses to a DDR2 SDRAM module is burst-oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed sequence. The burst length is
either four or eight locations. An auto precharge function can be enabled to provide a self-timed row precharge
that is initiated at the end of a burst access. The DDR2 SDRAM devices have a multibank architecture which
allows a concurrent operation that is providing a high effective bandwidth. A self refresh mode is provided and a
power-saving “power-down” mode. All inputs and all full drive-strength outputs are SSTL_18 compatible.
The DDR2 SDRAM module uses the serial presence detect (SPD) function implemented via serial EEPROM
using the standard I2C protocol. This nonvolatile storage device contains 256 bytes. The first 128 bytes are
utilized by the DIMM manufacturer (Swissbit) to identify the module type, the module’s organization and several
timing parameters. The second 128 bytes are available to the end user.
Module Configuration
Organization
256M x 72bit
DDR2 SDRAMs used
18 x 128M x 8bit (1024Mbit)
Row
Addr.
14
Device Bank
Select
Column
Addr.
Refresh
Module
Bank Select
BA0, BA1, BA2 10
8k S0#, S1#
Module Dimensions
in mm
133.33 (long) x 30(high) x 4 [max] (thickness)
Timing Parameters
Part Number
SEP02G72E2BF2SA-37R
SEP02G72E2BF2SA-30R
Module Density
2048 MB
2048 MB
Transfer Rate
4.2 GB/s
5.3 GB/s
Clock Cycle/Data bit
rate
3.7ns/533MT/s
3.0ns/667MT/s
Latency
4-4-4
5-5-5
Pin Name
A0 A13
BA0 BA2
DQ0 DQ63
CB0 CB7
DM0 DM8
DQS0 DQS8
DQS0# - DQS8#
RAS#
CAS#
WE#
CKE0 CKE1
CK0 CK1
CK0# - CK1#
S0#, S1#
Reset#
Address Inputs
Bank Address Inputs
Data Input / Output
Data check bits Input / Output
Input Data Mask
Data Strobe, positive line
Data Strobe, negative line (only used when differential data strobe mode is enabled)
Row Address Strobe
Column Address Strobe
Write Enable
Clock Enable
Clock Input, positive line
Clock Input, negative line
Chip Select
Asynchronously forces all registered outputs LOW when RESET# is LOW. This signal
can be used during power-up to ensure that CKE is LOW and DQs are High-Z.
Swissbit AG
Industriestrasse 4
CH 9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
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SEP02G72E2BF2SA-37R Даташит, Описание, Даташиты
PAR_IN
ERR_OUT
VDD / VDDQ
VREF
VSS
VDDSPD
SCL
SDA
SA0 SA2
ODT0, ODT1
NC
Data Sheet
Rev.1.0 23.11.2010
Parity bit for the address and control bus.
Parity error found on the address and control bus.
Supply Voltage (1.8V± 0.1V)
Input / Output Reference
Ground
Serial EEPROM Positive Power Supply
Serial Clock for Presence Detect
Serial Data Out for Presence Detect
Presence Detect Address Inputs
On-Die Termination
No Connection
Pin Configuration
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Front Side
VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
RESET
NC
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
Swissbit AG
Industriestrasse 4
CH 9552 Bronschhofen
PIN #
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
Back Side
VSS
DQ4
DQ5
VSS
DM0 (DQS9)
NC (DQS9#)
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1 (DQS10)
NC (DQS10#)
VSS
NC (CK1)
NC (CK1#)
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2 (DQS11)
NC (DQS11#)
VSS
DQ22
DQ23
VSS
PIN #
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
Front Side
A4
VDDQ
A2
VDD
VSS
VSS
VDD
Par_In
VDD
A10/AP
BA0
VDDQ
WE#
CAS#
VDDQ
NC (S1#)
NC (ODT1)
VDDQ
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
PIN #
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
Back Side
VDDQ
A3
A1
VDD
CK0
CK0#
VDD
A0
VDD
BA1
VDDQ
RAS#
S0#
VDDQ
ODT0
A13
VDD
VSS
DQ36
DQ37
VSS
DM4 (DQS13)
NC (DQS13#)
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DM5 (DQS14)
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SEP02G72E2BF2SA-37RSDRAM registered DIMMSwissbit
Swissbit

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