PDF NT5TU256M4DE-3C Data sheet ( Hoja de datos )

Número de pieza	NT5TU256M4DE-3C
Descripción	1Gb DDR2 SDRAM
Fabricantes	Nanya
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No Preview Available ! NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG 1Gb DDR2 SDRAM Feature CAS Latency Frequency Speed Sorts (CL-tRCD-tRP) Parameter Max. Clock Frequency tRCD tRP tRC tRAS tCK(Avg.)@CL3 tCK(Avg.)@CL4 tCK(Avg.)@CL5 tCK(Avg.)@CL6 tCK(Avg.)@CL7 DDR2-667 -3C 5-5-5 min max 125 333 15 - 15 - 60 - 45 70K 58 3.75 8 38 -- --  1.8V ± 0.1V Power Supply Voltage  8 internal memory banks  Programmable CAS Latency: 5 (DDR2-3C) 6 (DDR2-AD)  Programmable Additive Latency: 0, 1, 2, 3, 4 5  Write Latency = Read Latency -1  Programmable Burst Length:  4 and 8 Programmable Sequential / Interleave Burst  OCD (Off-Chip Driver Impedance Adjustment)  ODT (On-Die Termination)  4 bit prefetch architecture DDR2-800 -AD 6-6-6 min max 125 400 12.5 - 12.5 - 57.5 - 45 70K 58 Units tCK(Avg.) MHz ns ns ns ns ns 3.75 8 ns 2.5 8 ns 2.5 8 ns - - ns  Data-Strobes: Bidirectional, Differential  1KB page size for x4 and x8 2KB page size for x16  Strong and Weak Strength Data-Output Driver  Auto-Refresh and Self-Refresh  Power Saving Power-Down modes  7.8 µs max. Average Periodic Refresh Interval  RoHS Compliance  Packages:  60-Ball BGA for x4 / x8 components  84-Ball BGA for x16 components REV 1.0 06 / 2010 1 1 page NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG 1Gb DDR2 SDRAM Pin Configuration – 84 balls BGA Package (x16) 1 VDD DQ14 VDDQ DQ12 VDD DQ6 VDDQ DQ4 VDDL BA2 VSS VDD < TOP View> See the balls through the package 2 NC VSSQ DQ9 VSSQ NC VSSQ DQ1 VSSQ VREF CKE BA0 A10/ AP A3 A7 A12 3 VSS x 16 A UDM B VDDQ C DQ11 D VSS E LDM F VDDQ G DQ3 H VSS J WE K BA 1 L A1 M A5 N A9 P NC R 7 VSSQ UDQS VDDQ DQ10 VSSQ LDQS VDDQ DQ2 VSSDL RAS CAS A2 A6 A11 NC 8 UDQS VSSQ DQ8 VSSQ LDQS VSSQ DQ0 VSSQ C K CK CS A0 A4 A8 NC 9 VDDQ DQ15 VDDQ DQ13 VDDQ DQ7 VDDQ DQ5 VDD ODT VDD VSS REV 1.0 06 / 2010 5 5 Page NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG 1Gb DDR2 SDRAM Block Diagram (64Mb x 16) CKE CK CK CS WE CAS RAS 16 A0 – A12, BA0 – BA2 Control Logic Command Decode Mode Registers 16 13 10 Bank 7 Bank 6 13 Bank 5 Bank 4 Bank 3 RRoRLowBRDLowaB-RaDLowtaAeB-RcnaDLowtacAe-RhcnkadDLowtaocAe-RhcnkdDdLowtao&dcAe0-hckdDdLrowtao&dcAee1-ehcdDdLrwtaor&dcAee2s-ehcddrtaor&dcAeess-ehcddrtor&dcAessehcddror&dessehddrr&dessedrr&esserrssesss 8192 Decoder Bank 7 Bank 6 Bank 5 Bank 4 Bank 3 (81(M1(9S16M(eS2e16M3(mSnee1B63M8(Snseme163Mx84(oBaeSnseme16M384(BoeSrnsnea2me16AM384yxoeSrnsenamek6AM3584yx5oemrnsenkmeA38A4y6x51oemrn0skmAeA84pyx151oe2mrrsmAA4plyrxr251oe2mrxiAAarplyxfr51o2mrxaiAAirplyyxfr512mr6exy1aiAirplyfr512mrexy41ai6Airplfr12rexy1ai6A))irplfr2rexy1ai6)irlfrrexy1ai6)irfrexy1a6)irey16)r6) ) Sense Amplifier 13 8 16384 64 3 Bank Control Logic I/O Gating DM Mask Logic 256 (x64) Column 3 8 CDCoDCeolDCuceolDCumoceolDCumodceolnDCumodceeolnDumordceeolnumordceelnumordcenmordenrdenrer Decoder Column-Address Counter/Latch 8 2 COL0,1 CK, CK DLL 16 Data 16 64 16 16 MUX 16 DQS 4 Generator COL0,1 UDQS,  LDQS,  64 Mask Write FIFO & Drivers 8 Data 64 Input Register 22 22 22 22 2 16 16 16 16 16 16 16 16 16 Notes: 1. This Functional Block Diagram is intended to facilitate user understanding of the operation of the device; it does not represent an actual circuit implementation. 2. DM is an unidirectional signal (input only), but it is internally loaded to match the load of the bidirectional DQ and DQS signals. CK, CK COL0,1 4 ODT DQ0 – DQ15 UDQS, UDQS LDQS, LDQS UDM, LDM REV 1.0 06 / 2010 11 11 Page

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