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NT5TU128M8DE-3C PDF даташит

Спецификация NT5TU128M8DE-3C изготовлена ​​​​«Nanya» и имеет функцию, называемую «1Gb DDR2 SDRAM».

Детали детали

Номер произв NT5TU128M8DE-3C
Описание 1Gb DDR2 SDRAM
Производители Nanya
логотип Nanya логотип 

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NT5TU128M8DE-3C Даташит, Описание, Даташиты
NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Feature
CAS Latency Frequency
Speed Sorts
(CL-tRCD-tRP)
Parameter
Max. Clock Frequency
tRCD
tRP
tRC
tRAS
tCK(Avg.)@CL3
tCK(Avg.)@CL4
tCK(Avg.)@CL5
tCK(Avg.)@CL6
tCK(Avg.)@CL7
DDR2-667
-3C
5-5-5
min max
125 333
15 -
15 -
60 -
45 70K
58
3.75 8
38
--
--
1.8V ± 0.1V Power Supply Voltage
8 internal memory banks
Programmable CAS Latency:
5 (DDR2-3C)
6 (DDR2-AD)
Programmable Additive Latency: 0, 1, 2, 3, 4 5
Write Latency = Read Latency -1
Programmable Burst Length:
4 and 8 Programmable Sequential / Interleave Burst
OCD (Off-Chip Driver Impedance Adjustment)
ODT (On-Die Termination)
4 bit prefetch architecture
DDR2-800
-AD
6-6-6
min max
125 400
12.5 -
12.5 -
57.5 -
45 70K
58
Units
tCK(Avg.)
MHz
ns
ns
ns
ns
ns
3.75 8
ns
2.5 8
ns
2.5 8
ns
- - ns
Data-Strobes: Bidirectional, Differential
1KB page size for x4 and x8
2KB page size for x16
Strong and Weak Strength Data-Output Driver
Auto-Refresh and Self-Refresh
Power Saving Power-Down modes
7.8 µs max. Average Periodic Refresh Interval
RoHS Compliance
Packages:
60-Ball BGA for x4 / x8 components
84-Ball BGA for x16 components
REV 1.0
06 / 2010
1









No Preview Available !

NT5TU128M8DE-3C Даташит, Описание, Даташиты
NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Description
The 1giga-bit (1Gb) Double-Data-Rate-2 (DDR2) DRAMs is a high-speed CMOS Double Data Rate 2 SDRAM
containing 1,073,741,824 bits. It is internally configured as an octal-bank DRAM.
The 1Gb chip is organized as 32Mbit x 4 I/O x 8 bank, 16Mbit x 8 I/O x 8 bank or 8Mbit x 16 I/O x 8 bank device. These
synchronous devices achieve high speed double-data-rate transfer rates of up to 800 Mb/sec/pin for general appli-
cations.
The chip is designed to comply with all key DDR2 DRAM key features: (1) posted CAS with additive latency, (2) write
latency = read latency -1, (3) normal and weak strength data-output driver, (4) variable data-output impedance
adjustment and (5) an ODT (On-Die Termination) function.
All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are
latched at the cross point of differential clocks (CK rising and  falling). All I/Os are synchronized with a single ended
DQS or differential DQS pair in a source synchronous fashion. A 14 bit address bus for x4/x8 organized components
and A 13 bit address bus for x16 component is used to convey row, column, and bank address devices.
These devices operate with a single 1.8V ± 0.1V power supply and are available in BGA packages.
REV 1.0
06 / 2010
2









No Preview Available !

NT5TU128M8DE-3C Даташит, Описание, Даташиты
NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Pin Configuration 60 balls BGA Package (x4)
< TOP View>
See the balls through the package
1
VDD
NC
VDDQ
NC
VDDL
BA2
VSS
VDD
2
NC
VSSQ
DQ1
VSSQ
VREF
CKE
BA0
A10/ AP
A3
A7
A12
3
VSS
x4
A
7
VSSQ
DM B DQS
VDDQ C VDDQ
DQ3 D DQ2
VSS
E VSSDL
WE F RAS
BA1 G CAS
A1 H A2
A5 J A6
A9 K A11
NC L NC
8
DQS
VSSQ
DQ0
VSSQ
CK
CK
CS
A0
A4
A8
A13
9
VDDQ
NC
VDDQ
NC
VDD
ODT
VDD
VS
S
REV 1.0
06 / 2010
3










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Номер в каталогеОписаниеПроизводители
NT5TU128M8DE-3C1Gb DDR2 SDRAMNanya
Nanya

Номер в каталоге Описание Производители
TL431

100 мА, регулируемый прецизионный шунтирующий регулятор

Unisonic Technologies
Unisonic Technologies
IRF840

8 А, 500 В, N-канальный МОП-транзистор

Vishay
Vishay
LM317

Линейный стабилизатор напряжения, 1,5 А

STMicroelectronics
STMicroelectronics

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