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EDJ2116DEBG PDF даташит

Спецификация EDJ2116DEBG изготовлена ​​​​«Elpida Memory» и имеет функцию, называемую «2G bits DDR3 SDRAM».

Детали детали

Номер произв EDJ2116DEBG
Описание 2G bits DDR3 SDRAM
Производители Elpida Memory
логотип Elpida Memory логотип 

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EDJ2116DEBG Даташит, Описание, Даташиты
COVER
DATA SHEET
2G bits DDR3 SDRAM
EDJ2108DEBG (256M words × 8 bits)
EDJ2116DEBG (128M words × 16 bits)
Specifications
• Density: 2G bits
• Organization
— 32M words × 8 bits × 8 banks (EDJ2108DEBG)
— 16M words × 16 bits × 8 banks (EDJ2116DEBG)
• Package
— 78-ball FBGA (EDJ2108DEBG)
— 96-ball FBGA (EDJ2116DEBG)
— Lead-free (RoHS compliant) and Halogen-free
• Power supply: VDD, VDDQ = 1.5V ± 0.075V
• Data rate
— 2133Mbps/1866Mbps/1600Mbps/1333Mbps (max)
• Spread Spectrum Clock (SSC)
— Sweep rate: down spread 1% (20kHz to 60kHz)
• 1KB page size (EDJ2108DEBG)
— Row address: A0 to A14
— Column address: A0 to A9
• 2KB page size (EDJ2116DEBG)
— Row address: A0 to A13
— Column address: A0 to A9
• Eight internal banks for concurrent operation
• Interface: SSTL_15
• Burst length (BL): 8 and 4 with Burst Chop (BC)
• Burst type (BT):
— Sequential (8, 4 with BC)
— Interleave (8, 4 with BC)
• /CAS Latency (CL): 5, 6, 7, 8, 9, 10, 11, 13, 14
• /CAS Write Latency (CWL): 5, 6, 7, 8, 9, 10
• Precharge: auto precharge option for each burst
access
• Driver strength: RZQ/7, RZQ/6 (RZQ = 240)
• Refresh: auto-refresh, self-refresh
• Refresh cycles
— Average refresh period
7.8µs at 0°C TC +85°C
3.9µs at +85°C < TC +95°C
• Operating case temperature range
— TC = 0°C to +95°C
Features
• Double-data-rate architecture: two data transfers per
clock cycle
• The high-speed data transfer is realized by the 8 bits
prefetch pipelined architecture
• Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
the receiver
• DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK transitions
• Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
• Data mask (DM) for write data
• Posted /CAS by programmable additive latency for
better command and data bus efficiency
• On-Die Termination (ODT) for better signal quality
— Synchronous ODT
— Dynamic ODT
— Asynchronous ODT
• Multi Purpose Register (MPR) for pre-defined pattern
read out
• ZQ calibration for DQ drive and ODT
• /RESET pin for Power-up sequence and reset function
• SRT range:
— Normal/extended
• Programmable Output driver impedance control
• Seamless BL4 access with bank-grouping
— Applied only for DDR3-1333 and 1600
Document. No. E1712E60 (Ver. 6.0)
Date Published October 2013 (K) Japan
Printed in Japan
URL: http://www.elpida.com
©Elpida Memory, Inc. 2010-2013









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EDJ2116DEBG Даташит, Описание, Даташиты
EDJ2108DEBG, EDJ2116DEBG
Ordering Information
Part number
EDJ2108DEBG-MU-F
EDJ2108DEBG-JS-F
EDJ2108DEBG-GN-F
EDJ2108DEBG-DJ-F
EDJ2116DEBG-MU-F
EDJ2116DEBG-JS-F
EDJ2116DEBG-GN-F
EDJ2116DEBG-DJ-F
Die
revision
E
E
Organization
(words × bits)
256M × 8
128M × 16
Internal
banks
8
8
JEDEC speed bin
(CL-tRCD-tRP)
DDR3-2133 (14-14-14)
DDR3-1866 (13-13-13)
DDR3-1600 (11-11-11)
DDR3-1333 (9-9-9)
DDR3-2133 (14-14-14)
DDR3-1866 (13-13-13)
DDR3-1600 (11-11-11)
DDR3-1333 (9-9-9)
Package
78-ball FBGA
96-ball FBGA
Part Number
Elpida Memory
Type
D: Packaged Device
Product Family
J: DDR3
Density / Bank
21: 2Gb / 8-bank
Organization
08: x8
16: x16
Power Supply, Interface
D: 1.5V, SSTL_15
E D J 21 08 D E BG - MU - F
Environment code
F: Lead Free (RoHS compliant)
and Halogen Free
Speed
MU: DDR3-2133 (14-14-14)
JS: DDR3-1866 (13-13-13)
GN: DDR3-1600 (11-11-11)
DJ: DDR3-1333 (9-9-9)
Package
BG: FBGA
Die Rev.
Operating Frequency
Speed
Grade
Frequency (Mbps)
CL5 CL6 CL7
-MU 800 1066
-JS 667 800 1066
-GN 667 800 1066
-DJ 667 800 1066
CL8
1066
1066
1066
1066
CL9
1333
1333
1333
1333
CL10
1333
1333
1333
1333
CL11
1600
1600
1600
CL13
1866
1866
CL14
2133
speed bin
(CL-tRCD-tRP)
DDR3-2133
(14-14-14)
DDR3-1866
(13-13-13)
DDR3-1600
(11-11-11)
DDR3-1333
(9-9-9)
Detailed Information
For detailed electrical specification and further information, please refer to the DDR3 SDRAM General Functionality
and Electrical Condition data sheet (E1926E) and Addendum data sheet (E1928E).
Data Sheet E1712E60 (Ver. 6.0)
2









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EDJ2116DEBG Даташит, Описание, Даташиты
EDJ2108DEBG, EDJ2116DEBG
Pin Configurations
Pin Configurations (×8 configuration)
/xxx indicates active low signal.
78-ball FBGA
1 23
A
VSS VDD NC
B
VSS VSSQ DQ0
C
VDDQ DQ2 DQS
D
VSSQ DQ6 /DQS
E
VREFDQ VDDQ DQ4
F
NC VSS /RAS
G
ODT VDD /CAS
H
NC /CS /WE
J
VSS BA0 BA2
K
VDD A3
A0
L
VSS A5
A2
M
VDD A7
A9
N
VSS /RESET A13
789
NU/(/TDQS) VSS VDD
DM/TDQS VSSQ VDDQ
DQ1 DQ3 VSSQ
VDD VSS VSSQ
DQ7 DQ5 VDDQ
CK VSS NC
/CK VDD CKE
A10(AP) ZQ NC
NC VREFCA VSS
A12(/BC) BA1 VDD
A1 A4 VSS
A11 A6 VDD
A14 A8 VSS
(Top view)
Pin name
Function
Pin name
Function
A0 to A14*3
Address inputs
A10(AP): Auto precharge
A12(/BC): Burst chop
/RESET*3
Active low asynchronous reset
BA0 to BA2*3
Bank select
VDD
Supply voltage for internal circuit
DQ0 to DQ7
Data input/output
VSS
Ground for internal circuit
DQS, /DQS
Differential data strobe
VDDQ
Supply voltage for DQ circuit
TDQS, /TDQS
Termination data strobe
VSSQ
Ground for DQ circuit
/CS*3
Chip select
VREFDQ
Reference voltage for DQ
/RAS, /CAS, /WE*3
Command input
VREFCA
Reference voltage for CA
CKE*3
Clock enable
ZQ
Reference pin for ZQ calibration
CK, /CK
Differential clock input
NC*1
No connection
DM
Write data mask
NU*2
Not usable
ODT*3
ODT control
Notes: 1.
2.
3.
Not internally connected with die.
Don't connect. Internally connected.
Input only pins (address, command, CKE, ODT and /RESET) do not supply termination.
Data Sheet E1712E60 (Ver. 6.0)
3










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