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HC-55564 PDF даташит

Спецификация HC-55564 изготовлена ​​​​«Intersil Corporation» и имеет функцию, называемую «Continuously Variable Slope Delta-Modulator (CVSD)».

Детали детали

Номер произв HC-55564
Описание Continuously Variable Slope Delta-Modulator (CVSD)
Производители Intersil Corporation
логотип Intersil Corporation логотип 

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HC-55564 Даташит, Описание, Даташиты
Low Bit Rate Voiceband Encoders/Decoder
February
Semiconductor
1999
NO
Call
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HC-55564
Continuously Variable
Slope Delta-Modulator (CVSD)
[ /Title
(HC-
55564
)
/Sub-
ject
(Con-
tinu-
ously
Vari-
able
Slope
Delta-
Modu-
lator
(CVS
D))
/
Autho
r ()
/Key-
words
(Har-
ris
Semi-
con-
ductor
, Tele-
com,
SLICs
,
SLAC
s,
Tele-
phone,
Tele-
phony,
Features
Description
• All Digital
• Requires Few External Parts
• Low Power Drain: 1.5mW Typical From Single 4.5V
To 6V Supply
• Time Constants Determined by Clock Frequency;
No Calibration or Drift Problems: Automatic Offset
Adjustment
• Half Duplex Operation Under Digital Control
• Filter Reset Under Digital Control
• Automatic Overload Recovery
• Automatic “Quiet” Pattern Generation
• AGC Control Signal Available
Applications
• Voice Transmission Over Data Channels (Modems)
• Voice/Data Multiplexing (Pair Gain)
• Voice Encryption/Scrambling
• Voicemail
• Audio Manipulations: Delay Lines, Time Compression,
Echo Generation/Suppression, Special Effects, etc.
• Pagers/Satellites
• Data Acquisition Systems
• Voice I/O for Digital Systems and Speech Synthesis
Requiring Small Size, Low Weight, and Ease of
Reprogrammability
• Related Literature
- AN607, Delta Modulation for Voice Transmission
The HC-55564 is a half duplex modulator/demodulator CMOS
intergrated circuit used to convert voice signals into serial NRZ
digital data and to reconvert that data into voice. The conver-
sion is by delta-modulation, using the Continuously Variable
Slope (CVSD) method of modulation/demodulation.
While the signals are compatible with other CVSD circuits, the inter-
nal design is unique. The analog loop filters have been replaced by
very low power digital filters which require no external timing compo-
nents. This approach allows inclusion of many desirable features
which would be difficult to implement using other approaches.
The fundamental advantages of delta-modulation, along with its
simplicity and serial data format, provide an efficient (low data
rate/low memory requirements) method for voice digitization.
The HC-55564 is usable from 9kbits/s to above 64kbps. See the
Harris Military databook for a MIL-STD-883C compliant CVSD.
Application Note 607.
Ordering Information
PART
NUMBER
HC1-55564-2
HC1-55564-5
HC1-55564-9
HC3-55564-5
HC9P55564-5
TEMP.
RANGE (oC)
PACKAGE
PKG. NO.
-55 to 125 14 Ld CERDIP
F14.3
0 to 75 14 Ld CERDIP
F14.3
-40 to 85 14 Ld CERDIP
F14.3
0 to 75 14 Ld PDIP
E14.3
0 to 75 16 Ld Plastic SOIC (W) M16.3
Pinouts
HC-55564
(PDIP, CERDIP)
TOP VIEW
VDD 1
ANALOG GND 2
AOUT 3
AGC 4
AIN 5
NC 6
NC 7
14 DIG OUT
13 FZ
12 DIG IN
11 APT
10 ENC/DEC
9 CLOCK
8 DIG GND
HC-55564
(SOIC)
TOP VIEW
VDD 1
ANALOG GND 2
AOUT 3
AGC 4
AIN 5
NC 6
NC 7
NC 8
16 DIG OUT
15 FZ
14 DIG IN
13 APT
12 ENC/DEC
11 CLOCK
10 DIG GND
9 NC
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1999
1
File Number 2889.5









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HC-55564 Даташит, Описание, Даташиты
HC-55564
Absolute Maximum Ratings
Thermal Information
Voltage at Any Pin . . . . . . . . . . . . . . . . . . . .GND -0.3V to VDD 0.3V
Maximum VDD Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0V
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC
Operating Conditions
Temperature Range
HC-55564-5, -7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 750C
HC-55564-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 850C
HC-55564-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 1250C
Operating VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 6.0V
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
CERDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . .
70
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
85
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
98
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
Die Characteristics
Transistor Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1897
Die Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 x 82
Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +VDD
Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BiMOSE
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications Unless Otherwise Specified, typical parameters are at 25oC, Min-Max are over operating temperature
ranges. VDD = 5.0V, Sampling Rate = 16Kbps, AG = DG = 0V, AIN = 1.2VRMS
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Sampling Rate
CLK Note 2
9 16 64 kbps
Supply Current
Logic ‘1’ Input
Logic ‘0’ Input
Logic ‘1’ Output
Logic ‘0’ Output
Clock Duty Cycle
IDD
VIH Note 3
VIL Note 3
VOH Note 4
VOL Note 4
- 0.3 1.5 mA
3.5 -
-V
- - 1.5 V
4.0 -
-V
- - 0.4 V
30 - 70 %
Audio Input Voltage
Audio Output Voltage
Audio Input Impedance
Audio Output Impedance
Transfer Gain
Syllabic Filter Time Constant
Signal Estimate Filter Time
Constant
AIN
AOUT
ZIN
ZOUT
AE-D
tSF
tSE
AC Coupled (Note 5)
AC Coupled (Note 6)
Note 7
Note 7
No Load, Audio In to Audio Out.
Note 8
Note 8
- 0.5 1.2 VRMS
- 0.5 1.2 VRMS
- 280 - k
- 150 - k
-2.0 - +2.0 dB
- 4.0 - ms
1.0 -
- ms
Enc Threshold
AIN at 100Hz (Note 9), (Typ) 0.3% = 15mVRMS - 6 - mVPEAK
Minimum Step Size
MSS Note 10
- 0.1 - %VDD
Quieting Pattern Amplitude
VQP FZ = 0V or APT = 0V (Note 11)
- 10 - mVP-P
AGC Threshold
VATH
Note 12
- 0.1 - F.S.
Clamping Threshold
VCTH Note 13
- 0.75 - F.S.
NOTES:
2. There is one NRZ (Non-Return Zero) data bit per clock period. Data is clocked out on the negative clock edge. Data is clocked into the
CVSD on the positive going edge (see Figure 2). Clock may be run at less than 9kbps and greater than 64kbps.
3. Logic inputs are CMOS compatible at supply voltage and are diode protected. Digital data input is NRZ at clock rate.
4. Logic outputs are CMOS compatible at supply voltage and will withstand short-circuits to VDD or ground. Digital data output is NRZ and
changes with negative clock transitions. Each output will drive one LS TTL load.
5. Recommended voice input range for best voice performance. Should be externally AC coupled.
6. May be used for side-tone in encode mode. Should be externally AC coupled. Varies with audio input level by ±2dB.
7. Presents series impedance with audio signal. Zero signal reference is approximately VDD/2.
8. Note that filter time constants are inversely proportional to clock rate. Both filters approximate single pole responses.
9. The minimum audio input voltage above which encoding takes place.
10. The minimum audio output voltage change that can be produced by the internal DAC.
11. Settled value, the “quieting” pattern or idle-channel audio output steps at one-half the bit rate, changing state on negative clock transitions.
12. A logic “0” will appear at the AGC output pin when the recovered signal reaches one-half of full-scale value (positive or negative), i.e., at
VDD/2 ±25% of VDD.
13. The recovered signal will be clamped, and the computation will be inhibited, when the recovered signal reaches three-quarters of full-
scale value, and will unclamp when it falls below this value (positive or negative).
2









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HC-55564 Даташит, Описание, Даташиты
HC-55564
Pin Descriptions
PIN NUMBER
14 LEAD DIP
SYMBOL
DESCRIPTION
1 VDD Positive Supply Voltage. Voltage range is 4.5V to 6.0V.
2 Analog GND Analog Ground connection to D/A ladders and comparator.
3
AOUT
Audio Out recovered from 10-bit DAC. May be used as side tone at the transmitter. Presents
approximately 150ksource with DC offset of VDD/2. Within ±2dB of Audio Input. Should be ex-
ternally AC coupled.
4
AGC
Automatic Gain Control output. A logic low level will appear at this output when the recovered
signal excursion reaches one-half of full scale value. In each half cycle full scale is VDD/2. The
mark-space ratio is proportional to the average signal level.
5 AIN Audio Input to comparator. Should be externally AC coupled. Presents approximately 280kin
series with VDD/2.
6, 7 NC No internal connection is made to these pins.
8 Digital GND Logic ground. 0V reference for all logic inputs and outputs.
9
Clock
Sampling rate clock. In the decode mode, must be synchronized with the digital input data such
that the data is valid at the positive clock transition. In the encode mode, the digital data is clocked
out on the negative going clock transition. The clock rate equals the data rate.
10
Encode/
A single CVSD can provide half-duplex operation. The encode or decode function is selected by the
Decode
logic level applied to this input. A low level selects the encode mode, a high level the decode mode.
11 APT Alternate Plain Text input. Activating this input caused a digital quieting pattern to be transmitted, how-
ever; internally the CVSD is still functional and a signal is still available at the AOUT port. Active low.
12
Digital In
Input for the received digital NRZ data.
13 FZ Force Zero input. Activating this input resets the internal logic and forces the digital output and the
recovered audio output into the “quieting” condition. An alternating 1-0 pattern appears at the
digital output at 1/2 the clock rate. When this is decoded by a receive CVSD, a 10mVP-P inaudible
signal appears at audio output. Active low.
14
Digital Out
Output for transmitted digital NRZ data.
NOTE:
14. No active input should be left in a “floating condition.”
Functional Diagram (DIP Pin Numbers Shown)
(1)
VDD
(12)
DIGITAL
IN
3V TO 6V VDD
2
(5)
AIN
ZIN
(2)
ANALOG
GND
(3) AOUT
(SIDE TONE)
ZOUT
(4) AGC OUT
(10)
ENC/DEC
(11) (13) FORCE
APT
ZERO
(9)
CLOCK
(8) DIGITAL
GND
RESET
T F/F Q
(14)
DIGITAL
OUT
COMPARATOR
D 3 BIT
SHIFT
REGISTER
10 BIT
DAC
10
RESET
STEP
SIZE
LOGIC
10
10 BIT
DAC
SIGNAL 6 DIGITAL
ESTIMATE
MODULATOR
FILTER 1msec
±1
SYLLABIC
FILTER
4ms
RESET
3










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Номер в каталогеОписаниеПроизводители
HC-55564Continuously Variable Slope Delta-Modulator (CVSD)Intersil Corporation
Intersil Corporation

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