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HMP31GP7AFR4C-S5 Datasheet Download - Hynix

Номер произв HMP31GP7AFR4C-S5
Описание 240pin Registered DDR2 SDRAM DIMMs based on 2Gb
Производители Hynix
логотип Hynix логотип 



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HMP31GP7AFR4C-S5 Даташит, Описание, Даташиты
240pin Registered DDR2 SDRAM DIMMs based on 2Gb version A
This Hynix Registered Dual In-Line Memory Module (DIMM) series consists of 2Gb version A DDR2
SDRAMs in Fine Ball Grid Array (FBGA) packages on a 240pin glass-epoxy substrate. This Hynix 2Gb ver-
sion A based Registered DDR2 DIMM series provide a high performance 8 byte interface in 5.25" width
form factor of industry standard. It is suitable for easy interchange and addition.
FEATURES
• JEDEC standard Double Data Rate2 Synchro-
nous DRAMs (DDR2 SDRAMs) with 1.8V +/-
0.1V Power Supply
• All inputs and outputs are compatible with
SSTL_1.8 interface
• 8 Bank architecture
• Posted CAS
• Programmable CAS Latency 3, 4, 5, 6
• OCD (Off-Chip Driver Impedance Adjustment)
• ODT (On-Die Termination)
• Fully differential clock operations (CK & CK)
• Programmable Burst Length 4 / 8 with both
sequential and interleave mode
• Auto refresh and self refresh supported
• 8192 refresh cycles / 64ms
• Serial presence detect with EEPROM
• DDR2 SDRAM Package: 60 ball(x4/x8)
• 133.35 x 30.00 mm form factor
• RoHS compliant
ORDERING INFORMATION
Part Name
HMP31GP7AFR4C - Y5/S5/S6
Density
8GB
Organization
1G X 72
# of
DRAMs
36
# of
ranks
2
Parity
Support
O
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.1 / Jan. 2009
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HMP31GP7AFR4C-S5 Даташит, Описание, Даташиты
1240pin Registered DDR2 SDRAM DIMMs
SPEED GRADE & KEY PARAMETERS
Speed@CL3
Speed@CL4
Speed@CL5
Speed@CL6
CL-tRCD-tRP
Y5
(DDR2-667)
400
533
667
-
5-5-5
S6
(DDR2-800)
-
533
667
800
6-6-6
S5
(DDR2-800)
400
533
800
-
5-5-5
Unit
Mbps
Mbps
Mbps
Mbps
tCK
ADDRESS TABLE
Density Organization Ranks
8GB
1G x 72
2
SDRAMs
512Mb x 4
# of
DRAMs
36
# of row/bank/column Address
15(A0~A14)/3(BA0~BA2)/11(A0~A9,A11)
Refresh
Method
8K / 64ms
Rev. 0.1 / Jan. 2009
2







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HMP31GP7AFR4C-S5 Даташит, Описание, Даташиты
1240pin Registered DDR2 SDRAM DIMMs
Input/Output Functional Description
Symbol
CK0
CK0
CKE[1:0]
S[1:0]
ODT[1:0]
RAS, CAS, WE
Vref
VDDQ
BA[2:0]
A[9:0],A10/AP
A[13:11]
DQ[63:0],
CB[7:0]
DM[8:0]
VDD,VSS
DQS[17:0]
DQS[17:0]
SA[2:0]
SDA
SCL
VDDSPD
RESET
Par_In
Err_Out
TEST
Type Polarity
Pin Description
IN
Positive
Edge
Positive line of the differential pair of system clock inputs that drives input to the on-DIMM PLL.
IN
Negative Negative line of the differential pair of system clock inputs that drives input to the on-DIMM PLL.
Edge
IN
Active High
Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when low. By deactivat-
ing the clocks, CKE low initiates the Power Down mode or the Self Refresh mode.
Enables the associated DDR2 SDRAM command decoder when low and disables the command
IN Active Low decoder when high. When the command decoder is disabled, new commands are ignored but previous
operations continue. Rank 0 is selected by S0; Rank 1 is selected by S1
IN Active High On-Die Termination signals.
IN
Active Low
When sampled at the positive rising edge of the clock. RAS,CAS and WE(ALONG WITH S) define the
command being entered.
Supply
Reference voltage for SSTL18 inputs
Supply
Power supplies for the DDR2 SDRAM output buffers to provide improved noise immunity. For all current
DDR2 unbuffered DIMM designs, VDDQ shares the same power plane as VDD pins.
IN - Selects which DDR2 SDRAM internal bank of Eight is activated.
During a Bank Activate command cycle, Address input defines the row address(RA0~RA13)
During a Read or Write command cycle, Address input defines the column address when sampled at the
cross point of the rising edge of CK and falling edge of CK. In addition to the column address, AP is used
IN - to invoke auto precharge operation at the end of the burst read or write cycle. If AP is high., auto pre-
charge is selected and BA0-BAn defines the bank to be precharged. If AP is low, autoprecharge is dis-
abled. During a Precharge command cycle., AP is used in conjunction with BA0-BAn to control which
bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0-BAn
inputs. If AP is low, then BA0-BAn are used to define which bank to precharge.
IN - Data and Check Bit Input/Output pins.
DM is an input mask signal for write data. Input data is masked when DM is sampled High coincident with
IN Active High that input data during a write access. DM is sampled on both edges of DQS. Although DM pins are input
only, the DM loading matches the DQ and DQS loading.
Supply
Power and ground for the DDR2 SDRAM input buffers, and core logic. VDD and VDDQ pins are tied to
VDD/VDDQ planes on these modules.
IO
Positive
Edge
Positive line of the differential data strobe for input and output data
IO
Negative Negative line of the differential data strobe for input and output data
Edge
IN - These signals are tied at the system planar to either VSS or VDDSPD to configure the serial SPD
EEPROM address range.
This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A resister may be con-
I/O - nected from the SDA bus line to VDDSPD on the system planar to act as a pull up.
IN
-
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from
SCL to VDDSPD to act as a pull up on the system board.
Supply
Power supply for SPD EEPROM. This supply is separate from the VDD/VDDQ power plane. EEPROM
supply is operable from 1.7V to 3.6V.
The RESET pin is connected to the RST pin on the register and to the OE pin on the PLL. When low, all
IN register outputs will be driven low and the PLL clocks to the DRAMs and register(s) will be set to low
level (the PLL will remain synchronized with the input clock)
IN Parity bit for the Address and Control bus(“1”. Odd, “0”.Even)
OUT
Parity error found in the Address and Control bus
Used by memory bus analysis tools(unused on memory DIMMs)
Rev. 0.1 / Jan. 2009
3










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