PDF HMP31GP7AFR4C-S5 Data sheet ( Hoja de datos )

Número de pieza	HMP31GP7AFR4C-S5
Descripción	240pin Registered DDR2 SDRAM DIMMs based on 2Gb
Fabricantes	Hynix
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No Preview Available ! 240pin Registered DDR2 SDRAM DIMMs based on 2Gb version A This Hynix Registered Dual In-Line Memory Module (DIMM) series consists of 2Gb version A DDR2 SDRAMs in Fine Ball Grid Array (FBGA) packages on a 240pin glass-epoxy substrate. This Hynix 2Gb ver- sion A based Registered DDR2 DIMM series provide a high performance 8 byte interface in 5.25" width form factor of industry standard. It is suitable for easy interchange and addition. FEATURES • JEDEC standard Double Data Rate2 Synchro- nous DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power Supply • All inputs and outputs are compatible with SSTL_1.8 interface • 8 Bank architecture • Posted CAS • Programmable CAS Latency 3, 4, 5, 6 • OCD (Off-Chip Driver Impedance Adjustment) • ODT (On-Die Termination) • Fully differential clock operations (CK & CK) • Programmable Burst Length 4 / 8 with both sequential and interleave mode • Auto refresh and self refresh supported • 8192 refresh cycles / 64ms • Serial presence detect with EEPROM • DDR2 SDRAM Package: 60 ball(x4/x8) • 133.35 x 30.00 mm form factor • RoHS compliant ORDERING INFORMATION Part Name HMP31GP7AFR4C - Y5/S5/S6 Density 8GB Organization 1G X 72 # of DRAMs 36 # of ranks 2 Parity Support O This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.1 / Jan. 2009 1 1 page 1240pin Registered DDR2 SDRAM DIMMs PIN ASSIGNMENT Pin Name Pin Name Pin Name Pin Name Pin Name 1 VREF 41 VSS 81 DQ33 121 VSS 161 CB4 2 VSS 42 CB0 82 VSS 122 DQ4 162 CB5 3 DQ0 43 CB1 83 DQS4 123 DQ5 163 VSS 4 DQ1 44 VSS 84 DQS4 124 VSS 164 DM8,DQS17 5 VSS 45 DQS8 85 VSS 125 DM0/DQS9 165 DQS17 6 DQS0 46 DQS8 86 DQ34 126 DQS9 166 VSS 7 DQS0 47 VSS 87 DQ35 127 VSS 167 CB6 8 VSS 48 CB2 88 VSS 128 DQ6 168 CB7 9 DQ2 49 CB3 89 DQ40 129 DQ7 169 VSS 10 DQ3 50 VSS 90 DQ41 130 VSS 170 VDDQ 11 VSS 51 VDDQ 91 VSS 131 DQ12 171 NC,CKE1 12 DQ8 52 CKE0 92 DQS5 132 DQ13 172 VDD 13 DQ9 53 VDD 93 DQS5 133 VSS 173 A15,NC 14 VSS 54 BA2,NC 94 VSS 134 DM1/DQS10 174 A14,NC 15 DQS1 55 NC,Err_Out 95 DQ42 135 DQS10 175 VDDQ 16 DQS1 56 VDDQ 96 DQ43 136 VSS 176 A12 17 VSS 57 A11 97 VSS 137 RFU 177 A9 18 RESET 58 A7 98 DQ48 138 RFU 178 VDD 19 NC 59 VDD 99 DQ49 139 VSS 179 A8 20 VSS 60 A5 100 VSS 140 DQ14 180 A6 21 DQ10 61 A4 101 SA2 141 DQ15 181 VDDQ 22 DQ11 62 VDDQ 102 NC(TEST) 142 VSS 182 A3 23 VSS 63 A2 103 VSS 143 DQ20 183 A1 24 DQ16 64 VDD 104 DQS6 144 DQ21 184 VDD 25 DQ17 Key 105 DQS6 145 VSS Key 26 VSS 65 VSS 106 VSS 146 DM2/DQS11 185 CK0 27 DQS2 66 VSS 107 DQ50 147 DQS11 186 CK0 28 DQS2 67 VDD 108 DQ51 148 VSS 187 VDD 29 VSS 68 NC,Err_Out 109 VSS 149 DQ22 188 A0 30 DQ18 69 VDD 110 DQ56 150 DQ23 189 VDD 31 DQ19 70 A10/AP 111 DQ57 151 VSS 190 BA1 32 VSS 71 BA0 112 VSS 152 DQ28 191 VDDQ 33 DQ24 72 VDDQ 113 DQS7 153 DQ29 192 RAS 34 DQ25 73 WE 114 DQS7 154 VSS 193 S0 35 VSS 74 CAS 115 VSS 155 DM3/DQS12 194 VDDQ 36 DQS3 75 VDDQ 116 DQ58 156 DQS12 195 ODT0 37 DQS3 76 NC, S1 117 DQ59 157 VSS 196 A13,NC 38 VSS 77 NC, ODT1 118 VSS 158 DQ30 197 VDD 39 DQ26 78 VDDQ 119 SDA 159 DQ31 198 VSS 40 DQ27 79 VSS 120 SCL 160 VSS 199 DQ36 80 DQ32 200 DQ37 NC= No Connect, RFU= Reserved for Future Use. Note: 1. RESET(Pin 18) is connected to both OE of PLL and Reset of register. 2. NC/Err_out (Pin 55) and NC/Par_In(Pin68) are for optional function to check address and command parity. 3. The Test pin(Pin 102) is reserved for bus analysis probes and is not connected on normal memory modules(DIMMs) Pin 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 Name VSS DM4/DQS13 DQS13 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DM5/DQS14 DQS14 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS RFU RFU VSS DM6/DQS15 NC,DQS15 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DM7/DQS16 NC,DQS16 VSS DQ62 DQ63 VSS VDDSPD SA0 SA1 Rev. 0.1 / Jan. 2009 5 5 Page 1240pin Registered DDR2 SDRAM DIMMs PIN Capacitance (VDD=1.8V,VDDQ=1.8V, TA=25°C) 8GB: HMP31GP7AFR4C Pin CK0, /CK0 CKE, ODT /CS Address, /RAS, /CAS, /WE DQ, DM, DQS, /DQS Symbol CCK CI1 CI2 CI3 CIO Min TBD TBD TBD TBD TBD Max TBD TBD TBD TBD TBD Unit pF pF pF pF pF Rev. 0.1 / Jan. 2009 11 11 Page

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