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PDF HC109 Data sheet ( Hoja de datos )

Número de pieza HC109
Descripción Dual J-K Flip-Flop with Set and Reset
Fabricantes System Logic Semiconductor　
Logotipo System Logic Semiconductor Logotipo



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No Preview Available ! HC109 Hoja de datos, Descripción, Manual

SL74HC109
Dual J-K Flip-Flop with Set and Reset
High-Performance Silicon-Gate CMOS
The SL74HC109 is identical in pinout to the LS/ALS109. The device
inputs are compatible with standard CMOS outputs, with pullup
resistors, they are compatible with LS/ALSTTL outputs.
This device consists of two J-K flip-flops with individual set, reset,
and clock inputs. Changes at the inputs are reflected at the outputs
with the next low-to-high transition of the clock. Both Q to Q outputs
are available from each flip-flop.
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA
• High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION
SL74HC109N Plastic
SL74HC109D SOIC
TA = -55° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
PIN 16=VCC
PIN 8 = GND
FUNCTION TABLE
Inputs
Outputs
Set Reset Clock J K Q
Q
LH
X XX H
L
HL
LL
X XX L
H
X X X H* H*
HH
LL L
H
HH
H L Toggle
HH
L H No Change
HH
HH H
L
HH
L X X No Change
X = Don’t care
*Both outputs will remain high as long as Set and
Reset are low, but the output states are
unpredictable if Set and Reset go high
simultaneously.
S L S System Logic
Semiconductor

1 page




HC109 pdf
SL74HC109
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
Figure 3. Switching Waveforms
Figure 4. Test Circuit
EXPANDED LOGIC DIAGRAM
S L S System Logic
Semiconductor

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